Enhanced digital predistortion
First Claim
1. A method of pre-distorting a signal for input to an amplifier, comprising:
- generating a weight vector based on a pre-distorted input signal and an output signal of the amplifier using a computation reduction technique; and
pre-distorting an input signal for input to an amplifier based on the generated weight vector; and
wherein the computation reduction technique decomposes a number of multiplication operations between complex numbers such that a total number of multiplications and a total number of additions to generate the weight vector is reduced as compared to if the number of multiplication operations between complex numbers was not decomposed.
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Abstract
In one embodiment of the present invention, a weight vector is generated based on a pre-distorted input signal and an output signal of an amplifier using a computation reduction technique. The computation reduction technique decomposes a number of multiplication operations between complex numbers such that a number of multiplications and a number of additions to generate the weight vector is reduced as compared to if the number of multiplication operations between complex numbers was not decomposed. An input signal for input to an amplifier is pre-distorted based on the generated weight vector.
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Citations
17 Claims
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1. A method of pre-distorting a signal for input to an amplifier, comprising:
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generating a weight vector based on a pre-distorted input signal and an output signal of the amplifier using a computation reduction technique; and pre-distorting an input signal for input to an amplifier based on the generated weight vector; and wherein the computation reduction technique decomposes a number of multiplication operations between complex numbers such that a total number of multiplications and a total number of additions to generate the weight vector is reduced as compared to if the number of multiplication operations between complex numbers was not decomposed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification