Semiconductor device

• US 20070297214A1
• Filed: 06/04/2007
• Published: 12/27/2007
• Est. Priority Date: 06/09/2006
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Dembo, Hiroki
• Application Number:
  US11/806,738
• Publication Number:
  US 20070297214A1
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06K 19/0707 the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation G06K19/0702 takes precedence
• CPC Class Codes: G06K 19/0712 the arrangement being capable of triggering distinct operating modes or functions dependent on the strength of an energy or interrogation field in the proximity of the record carrier active means for hindering electromagnetic reading or writing G06K19/07336
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 7/10019 resolving collision on the communication channels between simultaneously or concurrently interrogated record carriers. collision between the communication channels used by wireless communication devices, where the solution is not particularly adapted for RFIDs or the like, H04W74/08
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

To provide a semiconductor device in which power consumption at the time of an anti-collision operation is reduced. A semiconductor device includes an arithmetic circuit, a storage device, and circuits for transmitting and receiving signals to and from the outside. The arithmetic circuit includes a central processing unit and a controller. The central processing unit executes a program for using the controller to reduce power consumption when a signal is transmitted to the outside. The program has a structure which includes a plurality of routines. Representatively, the program includes a command determination routine, a UID value processing routine, a mask value comparison routine, an N-slot power consumption reduction routine, an N-slot counter routine, and the like.

Claims

1. A semiconductor device comprising:

a central processing unit;

a controller;

a storage device; and

a circuit for transmitting and receiving signals to and from an outside,

wherein a program for using the controller to reduce power consumption of the central processing unit when a signal is transmitted to the outside is stored in the storage device.

2. The semiconductor device according to claim 1, wherein the controller stops the central processing unit when a signal is transmitted to the outside.

3. The semiconductor device according to claim 1, wherein the central processing unit executes the program to stop the central processing unit when a signal is transmitted to the outside.

4. The semiconductor device according to claim 1, wherein the program includes a plurality of routines.

5. The semiconductor device according to claim 4, wherein the plurality of routines includes a command determination routine, a unique identifier value processing routine, a mask value comparison routine, an N-slot counter routine, and an N-slot power consumption reduction routine.

6. The semiconductor device according to claim 4, wherein the plurality of routines reduces power consumption at a time of an anti-collision operation.

7. The semiconductor device according to claim 1, wherein the storage device includes a read-only memory and a random-access memory.

8. The semiconductor device according to claim 1, wherein the controller includes at least one selected from the group consisting of a CPU interface, a control register, a code extraction circuit, and an encoder circuit.

9. The semiconductor device according to claim 1, wherein the circuit for transmitting and receiving signals to and from the outside includes at least one selected from the group consisting of an antenna, a resonant circuit, a power supply circuit, a reset circuit, a clock generator circuit, a demodulation circuit, a modulation circuit, and a power supply generating circuit.

10. A semiconductor device comprising:

a central processing unit;

a controller;

a storage device; and

a circuit for transmitting and receiving signals to and from an outside,

wherein a program for using the controller to reduce power consumption of the central processing unit when a signal is transmitted to the outside is stored in the storage device, and

wherein execution of the program causes the controller to stop the central processing unit.

11. The semiconductor device according to claim 10, wherein the controller stops the central processing unit when a signal is transmitted to the outside.

12. The semiconductor device according to claim 10, wherein the central processing unit executes the program to stop the central processing unit when a signal is transmitted to the outside.

13. The semiconductor device according to claim 10, wherein the program includes a plurality of routines.

14. The semiconductor device according to claim 13, wherein the plurality of routines includes a command determination routine, a unique identifier value processing routine, a mask value comparison routine, an N-slot counter routine, and an N-slot power consumption reduction routine.

15. The semiconductor device according to claim 13, wherein the plurality of routines reduces power consumption at a time of an anti-collision operation.

16. The semiconductor device according to claim 10, wherein the storage device includes a read-only memory and a random-access memory.

17. The semiconductor device according to claim 10, wherein the controller includes at least one selected from the group consisting of a CPU interface, a control register, a code extraction circuit, and an encoder circuit.

18. The semiconductor device according to claim 10, wherein the circuit for transmitting and receiving signals to and from the outside includes at least one selected from the group consisting of an antenna, a resonant circuit, a power supply circuit, a reset circuit, a clock generator circuit, a demodulation circuit, a modulation circuit, and a power supply generating circuit.

19. A semiconductor device comprising:

a central processing unit;

a controller;

a storage device; and

a circuit for transmitting and receiving signals to and from an outside,

wherein a program for using the controller to reduce power consumption of the central processing unit when a signal is transmitted to the outside is stored in the storage device, and

wherein the central processing unit executes the program to stop the central processing unit.

20. The semiconductor device according to claim 19, wherein the controller stops the central processing unit when a signal is transmitted to the outside.

21. The semiconductor device according to claim 19, wherein the central processing unit executes the program to stop the central processing unit when a signal is transmitted to the outside.

22. The semiconductor device according to claim 19, wherein the program includes a plurality of routines.

23. The semiconductor device according to claim 22, wherein the plurality of routines includes a command determination routine, a unique identifier value processing routine, a mask value comparison routine, an N-slot counter routine, and an N-slot power consumption reduction routine.

24. The semiconductor device according to claim 22, wherein the plurality of routines reduces power consumption at a time of an anti-collision operation.

25. The semiconductor device according to claims 19, wherein the storage device includes a read-only memory and a random-access memory.

26. The semiconductor device according to claims 19, wherein the controller includes at least one selected from the group consisting of a CPU interface, a control register, a code extraction circuit, and an encoder circuit.

27. The semiconductor device according to claim 19, wherein the circuit for transmitting and receiving signals to and from the outside includes at least one selected from the group consisting of an antenna, a resonant circuit, a power supply circuit, a reset circuit, a clock generator circuit, a demodulation circuit, a modulation circuit, and a power supply generating circuit.