NONVOLATILE SEMICONDUCTOR MEMORY
First Claim
1. A nonvolatile semiconductor memory comprising:
- a source line side selection gate transistor that is having a first source region connected to a source line and a first gate electrode connected to a first select gate line;
a bit line side selection gate transistor that is having a second drain region connected to a bit line and a second gate electrode connected to a second select gate line;
a first memory cell string that is having a plurality of memory cell transistors connected in series, connected between a first drain region of the source line side selection gate transistor and a second source region of the bit line side selection gate transistor; and
a second memory cell string that is having a plurality of memory cell transistors connected in series, connected in parallel with the first memory cell string;
wherein the first memory cell string and the second memory cell string are stacked on a semiconductor substrate via an interlayer insulating film,wherein the source line side selection gate transistor and the bit line side selection gate transistor are placed on the semiconductor substrate.
1 Assignment
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Accused Products
Abstract
According to one embodiment, a nonvolatile semiconductor memory comprising: a source line side selection gate transistor that is having a first source region connected to a source line and a first gate electrode connected to a first select gate line; a bit line side selection gate transistor that is having a second drain region connected to a bit line and a second gate electrode connected to a second select gate line; a first memory cell string that is having a plurality of memory cell transistors connected in series, connected between a first drain region of the source line side selection gate transistor and a second source region of the bit line side selection gate transistor; and a second memory cell string that is having a plurality of memory cell transistors connected in series, connected in parallel with the first memory cell string; wherein the first memory cell string and the second memory cell string are stacked on a semiconductor substrate via an interlayer insulating film, wherein the source line side selection gate transistor and the bit line side selection gate transistor are placed on the semiconductor substrate.
161 Citations
20 Claims
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1. A nonvolatile semiconductor memory comprising:
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a source line side selection gate transistor that is having a first source region connected to a source line and a first gate electrode connected to a first select gate line; a bit line side selection gate transistor that is having a second drain region connected to a bit line and a second gate electrode connected to a second select gate line; a first memory cell string that is having a plurality of memory cell transistors connected in series, connected between a first drain region of the source line side selection gate transistor and a second source region of the bit line side selection gate transistor; and a second memory cell string that is having a plurality of memory cell transistors connected in series, connected in parallel with the first memory cell string; wherein the first memory cell string and the second memory cell string are stacked on a semiconductor substrate via an interlayer insulating film, wherein the source line side selection gate transistor and the bit line side selection gate transistor are placed on the semiconductor substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A nonvolatile semiconductor memory comprising:
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a source line side selection gate transistor that is having a first source region connected to a source line and a first gate electrode connected to a first select gate line; a bit line side selection gate transistor that is having a second drain region connected to a bit line and a second gate electrode connected to a second select gate line; a plurality of memory cell strings each having a plurality of memory cell transistors connected in series, the memory cell strings being connected in parallel between a first drain region of the source line side selection gate transistor and a second source region of the bit line side selection gate transistor. - View Dependent Claims (19, 20)
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Specification