Non-Volatile Memory And Method With Bit Line To Bit Line Coupled Compensation

• US 20070297234A1
• Filed: 08/31/2007
• Published: 12/27/2007
• Est. Priority Date: 09/17/2003
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Mehrdad Mofidi, Raul-Adrian Cernea, Shahzad Khalid, Yan Li
• Inventors: Mofidi, Mehrdad, Cernea, Raul-Adrian, Li, Yan, Khalid, Shahzad
• Granted Patent: US 7,532,514 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Abstract

When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

Claims

1. In a non-volatile memory having an array of memory storage units, each unit having a charge storage unit between a control gate and a channel region defined by a source and a drain, and a bit line switchably coupled to the drain, a method of programming a page of memory storage units having interconnected control gates to their target states, comprising:

(a) providing a bit line switchably coupled to the drain of each memory storage unit and a word line coupled to all the control gates of said page of memory storage units;

(b) applying an initial, first predetermined voltage to the bit lines of designated memory storage units of the page to enable programming;

(c) applying an initial, second predetermined voltage to the bit lines of un-designated memory storage units of said page to inhibit programming;

(d) floating the program-enabled bit lines, while raising the program-inhibited bit lines from said second predetermined voltage by a predetermined voltage difference to a third predetermined voltage, wherein a predetermined portion of the predetermined voltage difference is coupled as an offset to any neighboring, floated, program-enabled bit lines, and said third predetermined voltage enables floating of the channel of each program-inhibited memory storage unit; and

(e) applying a programming voltage pulse to the word line in order to program the designated memory storage units of the page, wherein those un-designated memory storage units of the page are program-inhibited by virtue of their floated channel boosted to a program inhibited voltage condition, and a perturbation resulted from the boosting on any neighboring program-enabled memory storage units is compensated by said offset.

2. The method as claim 1, wherein said floating the program-enabled bit lines precedes the floating of the channel of each program-inhibited memory storage unit.

3. The method as claim 1, wherein said floating the program-enabled bit lines is after the floating of the channel of each program-inhibited memory storage unit.

4. The method as claim 1, wherein said page of memory storage units forms a row of said array.

5. The method as claim 1, wherein said page of memory storage units forms a segment of a row of said array.

6. The method as claim 1, wherein:

said memory is organized as an array of NAND chains of memory storage units, each chain having a plurality of memory storage units connected in series, and said page of memory storage units is constituted from a memory storage unit from each NAND chain among a page thereof.

7. The method as claim 1, wherein each memory storage unit stores one bit of information.

8. The method as claim 1, wherein each memory storage unit stores more than one bit of information.

9. The method as claim 1, wherein said charge storage unit is a floating gate.

10. The method as claim 1, wherein said charge storage unit is a dielectric layer.

11. The method as claim 1, wherein said non-volatile memory is in the form of a card.

12. The method as claim 1, further comprising:

setting a program-enabled bit line to a predetermined potential that substantially maximizes programming efficiency whenever it has two neighboring bit lines that are also program-enabled.

13. The method as in claim 12, wherein said predetermined potential is at ground.

14. The method as in claim 1, further comprising:

(f) verifying the selected memory storage units under programming;

(g) re-designating any memory storage units that have not been verified; and

(h) repeating (c) to (g) until all of said page of memory storage units have been verified.

15. The method as claim 14, wherein said floating the program-enabled bit lines precedes the floating of the channel of each program-inhibited memory storage unit.

16. The method as claim 14, wherein said floating the program-enabled bit lines is after the floating of the channel of each program-inhibited memory storage unit.

17. The method as claim 14, wherein said page of memory storage units forms a row of said array.

18. The method as claim 14, wherein said page of memory storage units forms a segment of a row of said array.

19. The method as claim 14, wherein:

said memory is organized as an array of NAND chains of memory storage units, each chain having a plurality of memory storage units connected in series, and said page of memory storage units is constituted from a memory storage unit from each NAND chain among a page thereof.

20. The method as claim 14, wherein each memory storage unit stores one bit of information.

21. The method as claim 14, wherein each memory storage unit stores more than one bit of information.

22. The method as claim 14, wherein said charge storage unit is a floating gate.

23. The method as claim 14, wherein said charge storage unit is a dielectric layer.

24. The method as claim 14, wherein said non-volatile memory is in the form of a card.

25. The method as claim 14, further comprising:

setting a program-enabled bit line to a predetermined potential that substantially maximizes programming efficiency whenever it has two neighboring bit lines that are also program-enabled.

26. The method as in claim 25, wherein said predetermined potential is at ground.