Coherent Frequency Clock Generation and Spectrum Management With Non-Coherent Phase

• US 20070297550A1
• Filed: 06/22/2006
• Published: 12/27/2007
• Est. Priority Date: 06/22/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gilliland, Don A.
• Granted Patent: US 7,706,484 B2
• Time in Patent Office: Days
• US Class Current: 375/360
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents

Abstract

In a method for reducing electromagnetic interference in a clocked circuit, the clock circuit includes at least a first clock signal and a second clock signal. The method detects when a first transition of the first clock signal is substantially aligned with a corresponding second transition of the second clock signal. The second clock signal is delayed by a predetermined amount of time when the first transition is substantially aligned with the second transition.

Claims

1. A method for reducing electromagnetic interference in a clocked circuit, including at least a first clock signal and a second clock signal, comprising the steps of:

a. detecting when a first transition of the first clock signal is substantially aligned with a corresponding second transition of the second clock signal; and

b. when the first transition is substantially aligned with the second transition, then delaying the second clock signal by a predetermined amount of time.

2. The method of claim 1, wherein the detecting step comprises comparing a slope of the first transition to a slope of the second transition.

3. The method of claim 1, wherein the detecting step comprises comparing a transitional direction of the first transition to a transitional direction of the second transition.

4. The method of claim 1, wherein the detecting step comprises comparing a slope of the first transition to a slope of the second transition and comparing a transitional direction of the first transition to a transitional direction of the second transition.

5. The method of claim 1, wherein the second clock signal has a lower frequency than the first clock signal.

6. A method of reducing electromagnetic interference in a circuit between a first clock signal and a second clock signal, comprising the steps of:

a. delaying a selected one of the first clock signal and the second clock signal when the first clock signal exhibits a first transition that is substantially aligned with a second transition exhibited by the second clock signal; and

b. allowing the selected one of the first clock signal and the second clock signal to propagate normally when the first transition is not substantially aligned with the second transition.

7. The method of claim 6, wherein the delaying step comprises the step of passing the selected one of the first clock signal and the second clock signal into a delay line.

8. The method of claim 6, wherein the delaying step comprises the step of passing the selected one of the first clock signal and the second clock signal into a delay gate.

9. A clock management circuit, for managing at least a first clock signal and a second clock signal, comprising:

a. a first detector that detects a first transition of the first clock signal;

b. a second detector that detects a second transition of the second clock signal;

c. a first comparison circuit that compares the first transition to the second transition and that asserts a delay second signal when the first transition is in substantial alignment with the second transition; and

d. a first delay circuit that delays the second clock signal when the first delay signal is asserted.

10. The clock management circuit of claim 9, wherein the first detector comprises a phase detector.

11. The clock management circuit of claim 9, wherein the first delay circuit comprises a delay line through which the second clock signal propagates.

12. The clock management circuit of claim 9, wherein the first delay circuit comprises delay gate through which the second clock signal propagates.

13. The clock management circuit of claim 9, also adapted for managing a third clock signal and further comprising:

a. a third detector that detects a third transition of the third clock signal;

b. a second comparison circuit that compares the first transition to the third transition and that asserts a first delay third signal when the first transition is in substantial alignment with the third transition;

c. a second delay circuit that delays the third clock signal when the first delay third signal is asserted;

d. a third comparison circuit that compares the second transition to the third transition and that asserts a second delay third signal when the second transition is in substantial alignment with the third transition; and

e. a third delay circuit that delays the third clock signal when the second delay third signal is asserted.

14. The clock management circuit of claim 13, wherein the second detector and the third detector each comprise a phase detector.

15. The clock management circuit of claim 13, wherein the second delay circuit and the third delay circuit each comprise a delay line through which the third clock signal propagates.

16. The clock management circuit of claim 13, wherein the second delay circuit and the third delay circuit each comprise a delay gate through which the third clock signal propagates.