Vertical Field-Effect Transistor and Method of Forming the Same

• US 20070298559A1
• Filed: 06/19/2007
• Published: 12/27/2007
• Est. Priority Date: 06/21/2006
• Status: Active Grant

• Current Assignee: Flextronics International USA Incorporated (Flex, Ltd.)
• Original Assignee: Flextronics International USA Incorporated (Flex, Ltd.)
• Inventors: Ha, Wonill, Brar, Berinder P. S.
• Granted Patent: US 8,415,737 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/66848 with a Schottky gate, i.e. MESFET
• CPC Class Codes: H01L 29/8122 Vertical transistors SIT, PBT H01L29/7722
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer within the pillar regions. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.

Claims

1. A method of forming a semiconductor device, comprising:

forming a heavily doped substrate;

forming a source/drain contact below said heavily doped substrate;

forming a channel layer above said heavily doped substrate;

forming a heavily doped source/drain layer above said channel layer;

forming another source/drain contact above said heavily doped source/drain layer;

patterning and etching pillar regions through said another source/drain contact, said heavily doped source/drain layer, and portions of said channel layer to form a vertical cell;

forming non-conductive regions in said portions of said channel layer within said pillar regions; and

forming a gate above said non-conductive regions in said pillar regions.

2. The method as recited in claim 1 further comprising forming a heavily doped buffer layer on an upper surface of said heavily doped substrate before forming said channel layer.

3. The method as recited in claim 1 wherein said source/drain contacts are formed from an alloy including gold, germanium, and nickel and said gate is formed with platinum.

4. The method as recited in claim 1 wherein said heavily doped substrate is n-doped with silicon.

5. The method as recited in claim 1 wherein said channel layer is n-doped with silicon.

6. The method as recited in claim 1, further comprising:

forming a conformal dielectric layer across an upper surface of said semiconductor device and selectively removing portions thereof to form sidewall spacers within said pillar regions before forming said non-conductive regions; and

performing a wet etch on exposed surfaces of said semiconductor device to form undercut regions under said sidewall spacers before forming said non-conductive regions.

7. The method as recited in claim 1 wherein said heavily doped substrate forms a source, said source/drain contact forms a source contact, said heavily doped source/drain layer forms a drain and said another source/drain contact forms a drain contact of a vertical field-effect transistor.

8. The method as recited in claim 1 wherein said semiconductor device is a depletion mode device.

9. The method as recited in claim 1 wherein a doping density or a thickness of said channel layer is limited to form an enhancement mode device.

10. The method as recited in claim 1 further comprising forming a Schottky diode with said semiconductor device.

11. A semiconductor device, comprising:

a heavily doped substrate;

a source/drain contact below said heavily doped substrate;

a channel layer above said heavily doped substrate;

a heavily doped source/drain layer above said channel layer;

another source/drain contact above said heavily doped source/drain layer;

pillar regions through said another source/drain contact, said heavily doped source/drain layer, and portions of said channel layer to form a vertical cell therebetween;

non-conductive regions in said portions of said channel layer within said pillar regions; and

a gate above said non-conductive regions in said pillar regions.

12. The semiconductor device as recited in claim 11 further comprising a heavily doped buffer layer between said heavily doped substrate and said channel layer.

13. The semiconductor device as recited in claim 11 wherein said source/drain contacts are formed from an alloy including gold, germanium, and nickel and said gate is formed with platinum.

14. The semiconductor device as recited in claim 11 wherein said heavily doped substrate is n-doped with silicon.

15. The semiconductor device as recited in claim 11 wherein said channel layer is n-doped with silicon.

16. The semiconductor device as recited in claim 11 further comprising sidewall spacers on opposing sides of said vertical cell within said pillar regions, said gate being partially recessed in undercut regions under said sidewall spacers.

17. The semiconductor device as recited in claim 11 wherein said heavily doped substrate forms a source, said source/drain contact forms a source contact, said heavily doped source/drain layer forms a drain and said another source/drain contact forms a drain contact of a vertical field-effect transistor.

18. The semiconductor device as recited in claim 11 wherein said semiconductor device is a depletion mode device.

19. The semiconductor device as recited in claim 11 wherein a doping density or a thickness of said channel layer is limited to form an enhancement mode device.

20. The semiconductor device as recited in claim 11 further comprising a Schottky diode.

21. A power converter coupled to a source of electrical power and configured to provide a regulated output characteristic, comprising:

a semiconductor device forming a power switch, including;

a heavily doped substrate,

a source/drain contact below said heavily doped substrate,

a channel layer above said heavily doped substrate,

a heavily doped source/drain layer above said channel layer,

another source/drain contact above said heavily doped source/drain layer,

pillar regions through said another source/drain contact, said heavily doped source/drain layer, and portions of said channel layer to form a vertical cell therebetween,

non-conductive regions in said portions of said channel layer within said pillar regions, and

a gate above said non-conductive regions in said pillar regions;

a controller configured to control conduction intervals of said power switch to provide said regulated output characteristic; and

an output filter coupled to said power switch to filter said output characteristic.

22. The power converter as recited in claim 21 wherein said semiconductor device further includes a heavily doped buffer layer between said heavily doped substrate and said channel layer.

23. The power converter as recited in claim 21 wherein said source/drain contacts are formed from an alloy including gold, germanium and nickel and said gate is formed with platinum.

24. The power converter as recited in claim 21 wherein said heavily doped substrate is n-doped with silicon.

25. The power converter as recited in claim 21 wherein said channel layer is n-doped with silicon.

26. The power converter as recited in claim 21 wherein said semiconductor device further includes sidewall spacers on opposing sides of said vertical cell within said pillar regions, said gate being partially recessed in undercut regions under said sidewall spacers.

27. The power converter as recited in claim 21 wherein said heavily doped substrate forms a source, said source/drain contact forms a source contact, said heavily doped source/drain layer forms a drain and said another source/drain contact forms a drain contact of a vertical field-effect transistor.

28. The power converter as recited in claim 21 wherein said semiconductor device is a depletion mode device.

29. The power converter as recited in claim 21 wherein a doping density or a thickness of said channel layer is limited to form an enhancement mode device.

30. The power converter as recited in claim 21 wherein said semiconductor device further includes a Schottky diode parallel-coupled to said power switch.