Methods of Forming Integrated Circuitry, Methods of Forming Memory Circuitry, and Methods of Forming Field Effect Transistors
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Accused Products
Abstract
The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.
43 Citations
52 Claims
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1-20. -20. (canceled)
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21. A method of forming memory circuitry comprising:
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providing a silicon-comprising substrate comprising a memory array area and a peripheral circuitry area, the memory array area comprising a first pair of spaced adjacent electrically conductive structures received over the silicon-comprising substrate in at least a first cross-section of the substrate, the peripheral circuitry area comprising a second pair of spaced adjacent electrically conductive structures received over the silicon-comprising substrate in at least a second cross-section of the substrate, the conductive structures of the second pair being spaced further from one another in the second cross-section than are those of the first pair in the first cross-section;
depositing electrically conductive material between the conductive structures of each of the first and second pairs;
removing the conductive material effective to expose silicon between the conductive structures of the second pair in the second cross-section but not between the conductive structures of the first pair in the first cross-section; and
after the removing, depositing metal over the substrate and annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide between the conductive structures of the second pair in the second cross-section but not between the conductive structures of the first pair in the first cross-section. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A method of forming integrated circuitry comprising:
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providing a silicon-comprising substrate comprising a first circuitry area and a second circuitry area, the first circuitry area comprising a first pair of spaced adjacent gate electrodes received over the silicon-comprising substrate in at least a first cross-section of the substrate, spaced and facing anisotropically etched electrically insulative sidewall spacers being provided in the first cross-section between the gate electrodes of the first pair, the second circuitry area comprising a second pair of spaced adjacent gate electrodes received over the silicon-comprising substrate in at least a second cross-section of the substrate, spaced and facing anisotropically etched insulative sidewall spacers being provided in the second cross-section between the gate electrodes of the second pair, the facing anisotropically etched sidewall spacers between the second pair being spaced further from one another in the second cross-section than are those received between the first pair in the first cross-section;
depositing a masking material between the facing anisotropically etched sidewall spacers received between each of the first and second pairs of gate electrodes;
removing the masking material effective to expose silicon between the facing anisotropically etched sidewall spacers received between the second pair in the second cross-section but not between the facing anisotropically etched sidewall spacers received between the first pair in the first cross-section; and
after the removing, depositing metal over the substrate and annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide between the facing anisotropically etched sidewall spacers received between the second pair in the second cross-section but not between the facing anisotropically etched sidewall spacers received between the first pair in the first cross-section. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
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52-82. -82. (canceled)
Specification