Method for fabricating multiple FETs of different types

• US 20070298599A1
• Filed: 05/21/2007
• Published: 12/27/2007
• Est. Priority Date: 06/08/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jang, Se-Myeong, Yoshida, Makoto, Kahng, Jae-Rok, Lee, Chul, Kim, Keun-Nam, Jung, Kyoung-Ho, Sung, Hyun-ju, Kim, Hui-jung
• Granted Patent: US 7,700,445 B2
• Time in Patent Office: Days
• US Class Current: 438/585
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Abstract

For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.

Claims

1. A method of fabricating multiple field effect transistors (FETs), comprising:

depositing a first conductive layer over first and second active regions of a semiconductor substrate;

patterning the first conductive layer over the second active region to form mold structures;

forming at least one mask structure between the mold structures;

patterning the second active region such that a remaining portion of the semiconductor substrate under each of the at least one mask structure forms a respective fin of a second field effect transistor (FET); and

patterning the first conductive layer over the first active region to form a first gate of a first field effect transistor (FET).

2. The method of claim 1, further comprising:

forming a plurality of mask structures between the mold structures; and

patterning the second active region such that remaining portions of the semiconductor substrate under the mask structures forms multiple fins of the second FET.

3. The method of claim 2, further comprising:

forming a gate dielectric material on the fins; and

patterning a second conductive layer formed over the gate dielectric material to form a second gate of the second FET.

4. The method of claim 3, further comprising:

forming a conductive film between the gate dielectric material and the second conductive layer to adjust a threshold voltage of the second FET.

5. The method of claim 4, wherein the conductive film comprises titanium, tantalum, titanium nitride, or tantalum nitride.

6. The method of claim 3, further comprising:

implanting a dopant into the fins before forming the gate dielectric material.

7. The method of claim 3, further comprising:

depositing a third conductive layer on the first and second conductive layers;

patterning the first and third conductive layers to form the first gate of the first FET; and

patterning the second and third conductive layers to form the second gate of the second FET.

8. The method of claim 1, further comprising:

forming a buffer layer that remains over the first conductive layer in the first active region while the mold structures are being formed over the second active region.

9. The method of claim 1, further comprising:

forming a first gate dielectric material of the first FET between the first conductive layer and the substrate, wherein the first gate dielectric material and the first conductive layer are patterned over the substrate to form the first FET of a planar type.

10. The method of claim 1, further comprising:

forming a trench isolation structure that surrounds the first active region;

etching away portions of the trench isolation structure to expose side walls of the first active region to form a single fin of the first FET; and

forming a gate dielectric material at exposed surfaces of the semiconductor substrate in the first active region;

wherein the first conductive layer is formed on the gate dielectric material in the first active region.

11. The method of claim 10, further comprising:

forming the gate dielectric material also on an exposed surface of a third active region of the semiconductor substrate;

forming the first conductive layer also on the gate dielectric material in the third active region; and

patterning the gate dielectric material and the first conductive layer in the third active region to form another field effect transistor (FET) of a planar type.

12. A method of fabricating multiple field effect transistors (FETs), comprising:

depositing a first conductive layer over first and second active regions of a semiconductor substrate;

patterning the first conductive layer over the second active region to form mold structures;

forming spacers at sidewalls of the mold structures;

patterning the second active region such that remaining portions of the semiconductor substrate under the spacers form fins of a second field effect transistor (FET); and

patterning the first conductive layer over the first active region to form a first gate of a first field effect transistor (FET).

13. The method of claim 12, further comprising:

forming filling material between the spacers; and

etching away material surrounding the spacers over the second active region before the step of patterning the second active region.

14. The method of claim 12, further comprising:

forming a gate dielectric material on the fins; and

patterning a second conductive layer formed over the gate dielectric material to form a second gate of the second FET.

15. The method of claim 14, further comprising:

forming a conductive film between the gate dielectric material and the second conductive layer to adjust a threshold voltage of the second FET.

16. The method of claim 14, further comprising:

depositing a third conductive layer on the first and second conductive layers;

patterning the first and third conductive layers to form the first gate of the first FET; and

patterning the second and third conductive layers to form the second gate of the second FET.

17. The method of claim 12, further comprising:

forming a buffer layer that remains over the first conductive layer in the first active region while the spacers are being formed over the second active region.

18. The method of claim 12, further comprising:

forming a first gate dielectric material of the first FET between the first conductive layer and the substrate, wherein the first gate dielectric material and the first conductive layer are patterned over the substrate to form the first FET of a planar type.

19. The method of claim 12, further comprising:

forming a trench isolation structure that surrounds the first active region;

etching away portions of the trench isolation structure to expose side walls of the first active region to form a single fin of the first FET; and

forming a gate dielectric material at exposed surfaces of the semiconductor substrate in the first active region;

wherein the first conductive layer is formed on the gate dielectric material in the first active region.

20. The method of claim 19, further comprising:

forming the gate dielectric material also on an exposed surface of a third active region of the semiconductor substrate;

forming the first conductive layer also on the gate dielectric material in the third active region; and

patterning the gate dielectric material and the first conductive layer in the third active region to form another field effect transistor (FET) of a planar type.