USING MULTIPLE NON-VOLATILE MEMORY DEVICES TO STORE DATA IN A COMPUTER SYSTEM

• US 20070300007A1
• Filed: 06/21/2006
• Published: 12/27/2007
• Est. Priority Date: 06/21/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fish, Andrew J., Bulusu, Mallik, Rothman, Michael A., Zimmer, Vincent J.
• Granted Patent: US 7,406,560 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

Provided are a method, system, and machine readable medium for using multiple non-volatile memory devices to store data in a computer system. Access to a first and second memory devices are managed. The first memory device has faster read access and slower write access relative to the second memory device and the second memory device has slower read access and faster write access relative to the first memory device. Write requests to the first memory device are cached in the second memory device.

Claims

1. A method, comprising:

managing access to a first and second memory devices, wherein the first memory device has faster read access and slower write access relative to the second memory device and wherein the second memory device has slower read access and faster write access relative to the first memory device; and

caching write requests to the first memory device in the second memory device.

2. The method of claim 1, wherein the first and second memory devices comprise non-volatile memory devices.

3. The method of claim 2, wherein the first memory device comprises a NOR memory device and wherein the second memory device comprises a NAND memory device.

4. The method of claim 1, wherein caching write requests to the first memory device in the second memory device comprises:

receiving a write request of an update to target data;

writing the update to the second memory device;

invalidating a copy of the target data in the first memory device;

copying the target data from the second memory device including the update to the first memory device; and

invalidating the target data in the second memory device copied to the first memory device.

5. The method of claim 4, further comprising:

determining whether there is a copy of the target data in the first memory device, wherein the operations of invalidating the corresponding copy, copying the target data from the second memory device to the first memory device, and invalidating the target data are performed in response to determining that there is a copy of the target data in the first memory device, wherein data is not copied from the second memory device to the first memory device in response to determining that the copy of the target data is not included in the first memory device.

6. The method of claim 1, further comprising:

receiving a read request for data;

determining whether the requested data is within the first memory device;

accessing the requested data from the first memory device in response to determining that the requested data is in the first memory device; and

accessing the requested data from the second memory device in response to determining that the requested data is not in the first memory device.

7. The method of claim 1, wherein the first and second memory devices are included in a computer system and wherein the first memory device includes boot code executed during a power-on routine to initialize the computer system, and wherein the second memory device includes data that is not used during the power-on routine.

8. The method of claim 1, wherein the first and second memory devices are included in a computer system executing an operating system, further comprising:

providing a first interface to the operating system to enable the operating system to write data to the first memory device; and

providing a second interface to the operating system to enable the operating system to write data to the second memory device, wherein the first and second memory devices enable the operating system to retain data between power cycles.

9. A device in communication with a first and second memory devices, comprising:

management logic to manage access to the first and second memory devices, wherein the first memory device has faster read access and slower write access relative to the second memory device and wherein the second memory device has slower read access and faster write access relative to the first memory device; and

caching logic to cache write requests to the first memory device in the second memory device.

10. The device of claim 9, wherein the first and second memory devices comprise non-volatile memory devices.

11. The device of claim 10, wherein the first memory device comprises a NOR memory device and wherein the second memory device comprises a NAND memory device.

12. The device of claim 9, wherein the caching logic to cache write requests to the first memory device in the second memory device further:

receives a write request of an update to target data;

writes the update to the second memory device;

invalidates a copy of the target data in the first memory device;

copies the target data from the second memory device including the update to the first memory device; and

invalidates the target data in the second memory device copied to the first memory device.

13. The device of claim 12, wherein the caching logic to cache write requests further:

determines whether there is a copy of the target data in the first memory device, wherein the operations of invalidating the corresponding copy, copying the target data from the second memory device to the first memory device, and invalidating the target data are performed in response to determining that there is a copy of the target data in the first memory device, wherein data is not copied from the second memory device to the first memory device in response to determining that the copy of the target data is not included in the first memory device.

14. The device of claim 9, wherein the device further includes read request processing logic to:

receive a read request for data;

determine whether the requested data is within the first memory device;

access the requested data from the first memory device in response to determining that the requested data is in the first memory device; and

access the requested data from the second memory device in response to determining that the requested data is not in the first memory device.

22. The machine readable medium of claim 11, wherein the operations further:

determine whether there is a copy of the target data in the first memory device, wherein the operations of invalidating the corresponding copy, copying the target data from the second memory device to the first memory device, and invalidating the target data are performed in response to determining that there is a copy of the target data in the first memory device, wherein data is not copied from the second memory device to the first memory device in response to determining that the copy of the target data is not included in the first memory device.

15. A system, comprising:

a first and second memory devices;

a device in communication with the first and second memory devices, comprising;

management logic to manage access to the first and second memory devices, wherein the first memory device has faster read access and slower write access relative to the second memory device and wherein the second memory device has slower read access and faster write access relative to the first memory device; and

caching logic to cache write requests to the first memory device in the second memory device.

16. The system of claim 15, wherein the first memory device includes boot code to execute during a power-on routine to initialize the system, and wherein the second memory device includes data that is not used during the power-on routine.

17. The system of claim 15, further comprising:

an operating system;

a first interface to the operating system to enable the operating system to write data to the first memory device; and

a second interface to the operating system to enable the operating system to write data to the second memory device, wherein the first and second memory devices enable the operating system to retain data between power cycles.

18. A machine readable medium storing instructions that when executed causes the machine to perform operations with respect to a first and second memory devices and to further:

manage access to the first and second memory devices, wherein the first memory device has faster read access and slower write access relative to the second memory device and wherein the second memory device has slower read access and faster write access relative to the first memory device; and

cache write requests to the first memory device in the second memory device.

19. The machine readable medium of claim 18, wherein the first and second memory devices comprise non-volatile memory devices.

20. The machine readable medium of claim 19, wherein the first memory device comprises a NOR memory device and wherein the second memory device comprises a NAND memory device.

21. The machine readable medium of claim 18, wherein the operations to cache write requests to the first memory device in the second memory device further:

receive a write request of an update to target data;

write the update to the second memory device;

invalidate a copy of the target data in the first memory device;

copy the target data from the second memory device including the update to the first memory device; and

invalidate the target data in the second memory device copied to the first memory device.

23. The machine readable medium of claim 18, wherein the operations further:

receive a read request for data;

determine whether the requested data is within the first memory device;

access the requested data from the first memory device in response to determining that the requested data is in the first memory device; and

access the requested data from the second memory device in response to determining that the requested data is not in the first memory device.

24. The machine readable medium of claim 18, wherein the first and second memory devices are included in a computer system and wherein the first memory device includes boot code executed during a power-on routine to initialize the computer system, and wherein the second memory device includes data that is not used during the power-on routine.

25. The machine readable medium of claim 18, wherein the first and second memory devices are included in a computer system executing an operating system, wherein the operations further:

provide a first interface to the operating system to enable the operating system to write data to the first memory device; and

provide a second interface to the operating system to enable the operating system to write data to the second memory device, wherein the first and second memory devices enable the operating system to retain data between power cycles.