Memory System Including a Two-On-One Link Memory Subsystem Interconnection

• US 20070300018A1
• Filed: 06/27/2006
• Published: 12/27/2007
• Est. Priority Date: 06/27/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Campbell, John, Gower, Kevin
• Granted Patent: US 7,617,367 B2
• Time in Patent Office: Days
• US Class Current: 711/149
• CPC Class Codes: G06F 13/1673 using buffers

Abstract

A memory system including a first memory subsystem having a buffer device with a first port and a second port, one or more memory devices coupled to the buffer device via the second port, and a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller. The first two-on-one link is coupled to the first port of the buffer device. The first memory subsystem is configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device. The first two-on-one link includes up to two transceivers connected to a single link, with at least one of the up to two transceivers consisting of any one of two or more transmitters for transmitting signals or two or more receivers for receiving signals.

Claims

1. A memory system comprising:

a first memory subsystem comprising;

a buffer device having a first port and a second port;

one or more memory devices coupled to the buffer device via the second port; and

a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller, the first two-on-one link coupled to the first port of the buffer device, the first memory subsystem configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device and the first two-on-one link, wherein the first two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.

2. The memory system according to claim 1, wherein said first memory subsystem is one of a plurality of memory subsystems of said memory system and said first memory subsystem is disposed on a substrate separate from any other one of said plurality of memory subsystems.

3. The memory system of claim 1, wherein the first memory subsystem further includes a plurality of channels and a plurality of memory device select lines connected between the memory devices and the second port.

4. The memory system of claim 1 further comprising the memory controller, wherein the memory controller includes an interface, said interface including one or more memory subsystem ports for connecting to respective memory subsystems via a plurality of two-on-one links connected to respective memory subsystem ports of the plurality of memory subsystem ports, the plurality of two-on-one links including the first two-on-one link connecting the first port to a first memory subsystem port of the plurality of memory subsystem ports.

5. The memory system according to claim 4 further including a second two-on-one link having a connection to the controller and a third two-on-one link having a connection to the controller, wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.

6. The memory subsystem of claim 4, wherein the memory system further comprises:

the memory controller, wherein the one or more memory subsystem ports further comprises a second memory subsystem port;

a third buffer device having a first port and a second port;

one or more third memory devices coupled to the third buffer device via the second port on the third buffer device; and

a third two-on-one link coupled to the first port of the third buffer device and to the second port on the memory controller for providing communication between the second buffer device and the memory controller, wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link, wherein data is transferred between at least one memory device of the one or more third memory devices and the memory controller via the third buffer device and the third two-on-one link.

7. The memory system of claim 1, wherein the buffer device further includes a third port, the memory system further comprising:

a second buffer device having a first port and a second port;

a second two-on-one link having a first connection to the third port and a second connection to the first port of the second buffer device; and

one or more second memory devices connected to the second port of the second buffer device, wherein the memory subsystem is configured to transfer data between at least one memory device of the second one or more of memory devices and the memory controller via a path comprising the first buffer device, the first two-on-one link, the second buffer device and the second two-on-one link.

8. The memory system according to claim 7, wherein the second buffer device further includes a third port, the memory system further comprising:

a third buffer device having a first port and a second port;

a third two-on-one link having a first connection to the third port on the second buffer device and a second connection to the first port of the third buffer device; and

one or more second memory devices connected to the second port of the third buffer device, wherein the memory system is configured to transfer data between at least one memory device of the third one or more of memory devices and the memory controller via a path comprising the first buffer device, the first two-on-one link, the second buffer device, the second two-on-one link, the third buffer device and the third two-on-one link, wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.

9. The memory system according to claim 1, wherein the first two-on-one link further comprises a first link portion and a second link portion, said first and second link portions interconnected via a corresponding connector.

10. A memory subsystem comprising:

one or more repeater devices;

one or more two-on-one links, each two-on-one link having a first connection for connecting to a memory controller and a second connection connected to a respective repeater device of the one or more repeater devices; and

a plurality of repeater links, each repeater link having a first connection for connecting to a respective buffer device of a plurality of buffer devices and a second connection to the respective repeater device, wherein the memory subsystem is configured to transfer data between at least one memory device and the memory controller via a path comprising a buffer device, a repeater link, the respective repeater and the two-on-one link, wherein the two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.

11. The memory subsystem of claim 10 further comprising the memory controller connected to each respective repeater device via a respective two-on-one link.

12. The memory subsystem of claim 10 further comprising:

the memory controller connected to each respective repeater device via a respective two-on-one link;

a first plurality of buffer devices, each buffer device of the first plurality of buffer devices having an interface connected to a respective one or more memory devices, each buffer device of the first plurality of buffer devices having a second interface connected to said respective repeater device via said respective repeater link; and

a second plurality of buffer devices, each buffer device of the second plurality of buffer devices having an interface connected to a respective one or more second memory devices.

13. The memory subsystem according to claim 12, further comprising:

a second repeater device of the one or more repeater devices;

a second two-on-one link of the one or more two-on-one links having a first connection to the memory controller and a second connection to the second repeater device; and

a second plurality of repeater links, each repeater link in the second plurality of repeater links having a first connection to a respective buffer device of the second plurality of buffer devices and a second connection to the second repeater device.

14. The memory subsystem according to claim 13, wherein each of said repeater links consist of a corresponding two-on-one link wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.

15. The memory subsystem according to claim 12, wherein each of said repeater links consist of a corresponding two-on-one link wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.

16. A computer memory subsystem method comprising:

a memory controller receiving data from a buffer device at a memory subsystem port on a memory controller having a plurality of memory subsystem ports, the data received via a two-on-one link coupled to the buffer device, the buffer device having a first port coupled to one or more memory devices and a second port coupled to the two-on-one link wherein the data received at the memory controller is transferred from at least one of the memory devices to the memory controller via the buffer device and the two-on-one link, wherein the two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link;

transmitting data from the memory subsystem port on the memory controller to the first port on the buffer device via the two-on-one link; and

the at least one of the transceivers performs a function consisting of any one of receiving data by way of the two receivers or transmitting data by way of a selected one of said two transmitters.

17. The memory subsystem method according to claim 16, further including a plurality of substrates wherein each memory subsystem of the plurality of memory subsystems is disposed on a respective substrate of the plurality of substrates.

18. The memory subsystem method of claim 16 wherein the memory subsystem further includes a plurality of channels and a plurality of memory device select lines connected between the plurality of memory devices and the second port.

19. The memory subsystem method according to claim 16 further including a second two-on-one link having a connection to the controller and a third two-on-one link having a connection to the controller, wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.

20. The memory subsystem method of claim 16 comprising the further step of:

the memory controller receiving data to a second buffer device via a second two-on-one link and a second memory subsystem port on the memory controller; and

the memory controller transmitting data to a second buffer device via the second two-on-one link and a second memory subsystem port on the memory controller, wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.

21. The memory subsystem method of claim 16 wherein the buffer device further includes a third port in communication with a third buffer device via a third two-on-one link, the third buffer device having a first port coupled to one or more third memory devices and a second port coupled to the third two-on-one link comprising the further step of transferring data between one or more of the third memory devices and the memory controller via the third two-on-one link, the buffer device and the two-on-one link wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.

22. The memory subsystem method of claim 21 wherein the third buffer device further includes a third port in communication with a fourth buffer device via a fourth two-on-one link, the fourth buffer device having a first port coupled to one or more fourth memory devices and a second port coupled to the fourth two-on-one link comprising the further step of transferring data between one or more of the fourth memory devices and the memory controller via the fourth two-on-one link, the third buffer device and the third two-on-one link, the buffer device and the two-on-one link wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.

23. The memory subsystem method according to claim 16, wherein each two-on-one link further comprises a first link portion and a second link portion, said first and second link portions interconnected via a corresponding connector.

24. A computer memory subsystem method comprising:

a repeater device comprising a two-on-one link and a plurality of repeater links, the repeater device receiving first data from one of said repeater links and transmitting the first data to said two-on-one link;

the repeater device receiving second data from said two-on-one link and transmitting the second data to one of said repeater links, wherein the two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link, wherein the at least one of the transceivers performs a function consisting of any one of receiving data by way of the two receivers or transmitting data by way of a selected one of said two transmitters.

25. The method of claim 24 wherein the repeater device is in communication with a plurality of buffer devices via the plurality of repeater links comprising:

receiving said first data from a memory device at a buffer device;

transmitting said first data from said buffer device to said one of said repeater links;

a memory controller receiving said first data from said two-on-one link;

transmitting said second data from said memory controller to said two-on-one link;

said buffer device receiving said second data from said one of said repeater links; and

said buffer device transmitting said second data to said memory device.

26. The method of claim 25 further comprising:

a second repeater device comprising a second two-on-one link connected with the memory controller and a plurality of second repeater links, the repeater device receiving third data from one of said repeater links and transmitting the third data to said second two-on-one link;

the repeater device receiving fourth data from a second two-on-one link and transmitting the fourth data to one of said second repeater links wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link, wherein the at least one of the transceivers performs a function consisting of any one of receiving data by way of the two receivers or transmitting data by way of a selected one of said two transmitters.

27. The method according to claim 24, wherein each two-on-one link further comprises a first link portion and a second link portion, said first and second link portions interconnected via a corresponding connector.

28. A service for deploying two-on-one technology, the service comprising:

creating information for any one of making, using or selling two-on-one technology, the two-on-one technology comprising up to two transceivers, wherein the two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to the single chip die input pad for receiving signals via the single chip die input pad from the single link;

deploying said created information to one or more customers via a distribution process.

29. The service according to claim 28, wherein the information comprises any one of an ASIC chip die comprising said at least one of the transceivers, a two-on-one link design, a two-on-one link electrical characteristics, a two-on-one transceiver circuit or a two-on-one design rule wherein the information is distributed in a tangible form consisting of any one of an ASIC chip die, a hard copy document, a soft copy electronic document, an electronic transmission or via portable media, the portable media comprising any one of a CD, a DVD, magnetic tape, magnetic disk or FLASH memory.

30. A memory system comprising:

a memory controller having an interface that includes a plurality of memory subsystem ports;

a first memory subsystem including;

a buffer device having a first port and a second port, and

a plurality of memory devices coupled to the buffer device via the second port, wherein data is transferred between at least one memory device of the plurality of memory devices and the memory controller via the buffer device; and

a plurality of two-on-one links, each two-on-one link of the plurality of two-on-one links having a connection to a respective memory subsystem port of the plurality of memory subsystem ports, the plurality of two-on-one links including a first two-on-one link to connect the first port to a first memory subsystem port of the plurality of memory subsystem ports, wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.

31. The memory system according to claim 30, wherein the buffer device comprises the at least one transceiver, wherein the at least one transceiver consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.

32. A memory system comprising:

a controller device;

a first buffer device having a first interface and a second interface;

a second buffer device having a first interface and a second interface;

a first two-on-one link having a first connection to the controller device and a second connection to the first interface of the first buffer device;

a first plurality of memory devices connected to the second interface of the first buffer device;

a second two-on-one link having a first connection to the controller device and a second connection to the first interface of the second buffer device; and

a second plurality of memory devices connected to the second interface of the second buffer device wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.

33. The memory system of claim 32, wherein the first buffer device further includes a third interface, the memory system further including:

a third buffer device having a first interface and a second interface;

a third two-on-one link having a first connection to the third interface and a second connection to the first interface of the third buffer device; and

a third plurality of memory devices connected to the second interface of the third buffer device wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.