Memory System Including a Two-On-One Link Memory Subsystem Interconnection
First Claim
1. A memory system comprising:
- a first memory subsystem comprising;
a buffer device having a first port and a second port;
one or more memory devices coupled to the buffer device via the second port; and
a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller, the first two-on-one link coupled to the first port of the buffer device, the first memory subsystem configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device and the first two-on-one link, wherein the first two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link.
1 Assignment
0 Petitions
Accused Products
Abstract
A memory system including a first memory subsystem having a buffer device with a first port and a second port, one or more memory devices coupled to the buffer device via the second port, and a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller. The first two-on-one link is coupled to the first port of the buffer device. The first memory subsystem is configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device. The first two-on-one link includes up to two transceivers connected to a single link, with at least one of the up to two transceivers consisting of any one of two or more transmitters for transmitting signals or two or more receivers for receiving signals.
-
Citations
33 Claims
-
1. A memory system comprising:
a first memory subsystem comprising;
a buffer device having a first port and a second port;
one or more memory devices coupled to the buffer device via the second port; and
a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller, the first two-on-one link coupled to the first port of the buffer device, the first memory subsystem configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device and the first two-on-one link, wherein the first two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
10. A memory subsystem comprising:
-
one or more repeater devices;
one or more two-on-one links, each two-on-one link having a first connection for connecting to a memory controller and a second connection connected to a respective repeater device of the one or more repeater devices; and
a plurality of repeater links, each repeater link having a first connection for connecting to a respective buffer device of a plurality of buffer devices and a second connection to the respective repeater device, wherein the memory subsystem is configured to transfer data between at least one memory device and the memory controller via a path comprising a buffer device, a repeater link, the respective repeater and the two-on-one link, wherein the two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link. - View Dependent Claims (11, 12, 13, 14, 15)
-
-
16. A computer memory subsystem method comprising:
-
a memory controller receiving data from a buffer device at a memory subsystem port on a memory controller having a plurality of memory subsystem ports, the data received via a two-on-one link coupled to the buffer device, the buffer device having a first port coupled to one or more memory devices and a second port coupled to the two-on-one link wherein the data received at the memory controller is transferred from at least one of the memory devices to the memory controller via the buffer device and the two-on-one link, wherein the two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link;
transmitting data from the memory subsystem port on the memory controller to the first port on the buffer device via the two-on-one link; and
the at least one of the transceivers performs a function consisting of any one of receiving data by way of the two receivers or transmitting data by way of a selected one of said two transmitters. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
-
-
24. A computer memory subsystem method comprising:
-
a repeater device comprising a two-on-one link and a plurality of repeater links, the repeater device receiving first data from one of said repeater links and transmitting the first data to said two-on-one link;
the repeater device receiving second data from said two-on-one link and transmitting the second data to one of said repeater links, wherein the two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link, wherein the at least one of the transceivers performs a function consisting of any one of receiving data by way of the two receivers or transmitting data by way of a selected one of said two transmitters. - View Dependent Claims (25, 26, 27)
-
-
28. A service for deploying two-on-one technology, the service comprising:
-
creating information for any one of making, using or selling two-on-one technology, the two-on-one technology comprising up to two transceivers, wherein the two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to the single chip die input pad for receiving signals via the single chip die input pad from the single link;
deploying said created information to one or more customers via a distribution process. - View Dependent Claims (29)
-
-
30. A memory system comprising:
-
a memory controller having an interface that includes a plurality of memory subsystem ports;
a first memory subsystem including;
a buffer device having a first port and a second port, and a plurality of memory devices coupled to the buffer device via the second port, wherein data is transferred between at least one memory device of the plurality of memory devices and the memory controller via the buffer device; and
a plurality of two-on-one links, each two-on-one link of the plurality of two-on-one links having a connection to a respective memory subsystem port of the plurality of memory subsystem ports, the plurality of two-on-one links including a first two-on-one link to connect the first port to a first memory subsystem port of the plurality of memory subsystem ports, wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link. - View Dependent Claims (31)
-
-
32. A memory system comprising:
-
a controller device;
a first buffer device having a first interface and a second interface;
a second buffer device having a first interface and a second interface;
a first two-on-one link having a first connection to the controller device and a second connection to the first interface of the first buffer device;
a first plurality of memory devices connected to the second interface of the first buffer device;
a second two-on-one link having a first connection to the controller device and a second connection to the first interface of the second buffer device; and
a second plurality of memory devices connected to the second interface of the second buffer device wherein each two-on-one link comprises up to two transceivers connected to a single link, wherein at least one of the up to two transceivers consists of any one of two or more transmitters on a single chip die connected to a single chip die output pad for transmitting signals via the single chip die output pad over the single link or two or more receivers on the single chip die connected to a single chip die input pad for receiving signals via the single chip die input pad from the single link. - View Dependent Claims (33)
-
Specification