Mechanism for Windaging of a Double Rate Driver
First Claim
1. A method for launching synchronous data from two sources on chip to a double data rate bus, including the steps of:
- coupling said two sources as inputs to a multiplexer that couples first one source then the other source to the bus on each edge of a select signal operating at a local clock signal rate;
delaying the select signal with a programmable delay element.
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Accused Products
Abstract
A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.
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Citations
12 Claims
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1. A method for launching synchronous data from two sources on chip to a double data rate bus, including the steps of:
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coupling said two sources as inputs to a multiplexer that couples first one source then the other source to the bus on each edge of a select signal operating at a local clock signal rate; delaying the select signal with a programmable delay element. - View Dependent Claims (2, 3, 4)
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5. A system for launching synchronous data from two sources on chip to a double data rate bus, comprising in combination:
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means for coupling said two sources as inputs to a multiplexer that couples first one source then the other source to the bus on each edge of a select signal operating at a local clock signal rate; programmable means for delaying the select signal. - View Dependent Claims (6, 7, 8)
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9. A chip that launches synchronous data from two sources on the chip to a double data rate bus, comprising in combination:
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a multiplexer that couples first one source then the other source to the bus on each edge of a select signal operating at a local clock signal rate; a programmable delay element for delaying the select signal. - View Dependent Claims (10, 11, 12)
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Specification