Mechanism for Windaging of a Double Rate Driver

• US 20070300098A1
• Filed: 06/27/2006
• Published: 12/27/2007
• Est. Priority Date: 06/27/2006
• Status: Active Grant

• Current Assignee: X Corp. (f/k/a Twitter, Inc.) (X Holdings Corp.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Jonathan Y., Magee, Jeffrey A., Webber, David A.
• Granted Patent: US 7,734,944 B2
• Time in Patent Office: Days
• US Class Current: 713/401
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators

Abstract

A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.

Claims

1. A method for launching synchronous data from two sources on chip to a double data rate bus, including the steps of:

coupling said two sources as inputs to a multiplexer that couples first one source then the other source to the bus on each edge of a select signal operating at a local clock signal rate;

delaying the select signal with a programmable delay element.

2. A method for launching synchronous data from two sources on chip to a double data rate bus as in claim 1 including the further step of delaying one of the input of one of sources with a delay element whose delay is a function of the local clock signal.

3. A method for launching synchronous data from two registers on a chip to a double data rate bus as in claim 1 including the further step of generating from a local clock signal two clock signals, one to clock one of said two registers, and the other to clock the other one of said two registers.

4. A method for launching synchronous data from two sources on chip to a double data rate bus as in claim 3, including the further step of delaying one of the input of one of sources with a delay element whose delay is a function of the local clock signal.

5. A system for launching synchronous data from two sources on chip to a double data rate bus, comprising in combination:

means for coupling said two sources as inputs to a multiplexer that couples first one source then the other source to the bus on each edge of a select signal operating at a local clock signal rate;

programmable means for delaying the select signal.

6. A system for launching synchronous data from two sources on chip to a double data rate bus as in claim 5 including means for delaying one of the input of one of sources with a delay element whose delay is a function of the local clock signal.

7. A system for launching synchronous data from two registers on a chip to a double data rate bus as in claim 5 including means for generating from a local clock signal two clock signals, means to couple one clock signal to one of said two registers, and means to couple the other clock signal to clock the other one of said two registers.

8. A system for launching synchronous data from two registers on a chip to a double data rate bus as in claim 6 including means for generating from a local clock signal two clock signals, means to couple one clock signal to one of said two registers, and means to couple the other clock signal to clock the other one of said two registers.

9. A chip that launches synchronous data from two sources on the chip to a double data rate bus, comprising in combination:

a multiplexer that couples first one source then the other source to the bus on each edge of a select signal operating at a local clock signal rate;

a programmable delay element for delaying the select signal.

10. A chip that launches synchronous data from two sources on the chip to a double data rate bus as in claim 9 including a delay element whose delay is a function of the local clock signal frequency that delays one of the input from one of sources.

11. A chip that launches synchronous data from two registers on the chip to a double data rate bus as in claim 9 including a clock generator generating from a local clock signal two clock signals, means to couple one clock signal to one of said two registers, and means to couple the other clock signal to clock the other one of said two registers.

12. A chip that launches synchronous data from two registers on the chip to a double data rate bus as in claim 10 including a clock generator generating from a local clock signal two clock signals, means to couple one clock signal to one of said two registers, and means to couple the other clock signal to clock the other one of said two registers.