Phase shifter with reduced linear dependency

• US 20070300110A1
• Filed: 08/27/2007
• Published: 12/27/2007
• Est. Priority Date: 11/23/1999
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Rajski, Janusz, Tyszer, Jerzy, Tamarapalli, Nagesh
• Granted Patent: US 7,523,372 B2
• Time in Patent Office: Days
• US Class Current: 714/728
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552

Abstract

A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

Claims

1-19. -19. (canceled)

20. A method, comprising:

providing an integrated circuit to be tested, the integrated circuit capable of receiving test patterns;

providing a linear finite state machine (LFSM) having a substantially balanced load; and

generating a linear phase shifter, the linear phase shifter working in combination with the LFSM to send a plurality of test patterns to the integrated circuit to be tested.

21. The method of claim 20, wherein generating the linear phase shifter comprises selecting cells of the LFSM by using a pseudo-random number generator yielding uniformly distributed integers between 0 and n−

1, wherein n represents the size of the LFSM.

22. The method of claim 21, wherein selecting cells comprises consulting a histogram of the cells to determine how often the cells have been used.

23. The method of claim 21, wherein selecting cells further comprises given a first cell, temporarily excluding the first cell if a number of times the first cell has been used exceeds a given threshold.

24. The method of claim 20, wherein generating the linear phase shifter comprises:

generating a linear combination of taps; and

verifying that test patterns produced by the linear combination of taps do not overlap with sequences generated by at least one previously generated combination of taps.

25. The method of claim 20, wherein the substantially balanced load includes memory elements of the LFSM driving a substantially similar number of linear logic gates in the linear phase shifter.

26. The method of claim 20, further including generating test patterns to be loaded in scan chains using the LFSM and the phase shifter and ensuring a phase shift of the test patterns from the linear phase shifter outputs is greater than a length of the longest scan chain.

27. One or more computer-readable media having computer-executable instructions for performing the method of claim 20.

28. A linear finite state machine and phase shifter combination, comprising:

a linear finite state machine including a plurality of memory elements coupled in series; and

a phase shifter including a plurality of logic gates coupled to selected memory elements of the linear finite state machine,

each of the selected memory elements being coupled to a substantially similar number of logic gates in the phase shifter.

29. The linear finite state machine and phase shifter combination of claim 28, wherein the memory elements have substantially balanced loading.

30. The linear finite state machine and phase shifter combination of claim 28, wherein the memory elements are coupled in a ring structure with intermediate feedback elements.

31. The linear finite state machine and phase shifter combination of claim 28, wherein the logic gates include XOR gates, XNOR gates, or both XOR and XNOR gates.

32. The linear finite state machine and phase shifter combination of claim 28, wherein the memory elements include flip-flops.

33. One or more computer-readable media storing circuit design information for implementing the apparatus of claim 28.

34. One or more computer-readable media storing computer-executable instructions for causing a computer to synthesize the apparatus of claim 28.

35. An apparatus comprising:

means for generating test patterns to test an integrated circuit, the means for generating having a balanced load on its outputs; and

means for phase shifting the generated test patterns.

36. The apparatus of claim 35, further including means for receiving the phase shifted test patterns for testing the integrated circuit.

37. The apparatus of claim 35, wherein the means for generating includes intermediate feedback means.

38. The apparatus of claim 35, wherein the means for phase shifting includes a plurality of XOR or XNOR gates having multiple inputs coupled to the means for generating.

39. One or more computer-readable media storing circuit design information for implementing the apparatus of claim 35.

40. One or more computer-readable media storing computer-executable instructions for causing a computer to synthesize the apparatus of claim 35.