MANAGING EXECUTION OF MIXED WORKLOADS IN A SIMULTANEOUS MULTI-THREADED (SMT) ENABLED SYSTEM

• US 20070300227A1
• Filed: 06/27/2006
• Published: 12/27/2007
• Est. Priority Date: 06/27/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mall, Michael G., Moody, James B., Warrier, Suresh E.
• Granted Patent: US 8,136,111 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 2209/5018 Thread allocation
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals

Abstract

A method, system, and program are provided for managing execution of mixed workloads in a simultaneous multi-threaded (SMT) enabled system. In one embodiment, in a SMT enabled processor system, having multiple processors each activated to interleave execution of multiple hardware threads on each processor, for ST workload, the kernel of the SMT enabled processor system facilitates construction of an exclusive set of processors to simulate an ST mode for handling the tasks of the ST workload, wherein the ST workload runs more efficiently on single threaded processors. The kernel schedules the ST workload on the exclusive set of processors by selecting one hardware thread per processor within said exclusive set of processors to handle a separate one of the tasks of the ST workload, while requiring the remaining hardware threads per processor within the exclusive set to idle. As a result, the ST workload is executed on the SMT enabled processor system as if the exclusive set of processors run in ST mode, but without actually deactivating the remaining idle hardware threads per processor within the exclusive set of processors.

Claims

1. A method for managing a simultaneous multi-threaded (SMT) enabled processor system comprising a plurality of processors each activated to simultaneously execute a plurality of hardware threads, said method comprising:

facilitating construction of an exclusive set of processors from among said plurality of processors to handle a plurality of tasks of an single-threaded (ST) workload in said SMT enabled processing system; and

scheduling said ST workload on said exclusive set of processors by selecting only one hardware thread per processor within said exclusive set of processors to handle a separate one of said plurality of tasks of the ST workload while requiring the remaining hardware threads per processor within said exclusive set of processors to idle, such that said ST workload is executed on an SMT enabled processor system as if said exclusive set of processors are running in ST mode without deactivating the remaining idle hardware threads per processor within said exclusive set of processors.

2. The method according to claim 1 further comprising:

setting a separate dispatcher for each hardware thread of said exclusive set of processors to only execute work on each local run queue associated with each said hardware thread of said exclusive set of processors;

draining any tasks waiting on each local run queue associated with each said hardware thread of said exclusive set of processors;

responsive to placing each said hardware thread of said exclusive set of processors in an idle mode without any tasks to perform, setting each said hardware thread of said exclusive set of processors in a snooze mode, wherein only an interrupt awakens each said hardware thread placed in snooze mode to search an associated local run queue for waiting tasks;

applying each separate task of said ST workload to a separate local run queue of each said selected one hardware thread per processor within said exclusive set of processors;

sending an interrupt to wake up said selected one hardware thread per processor.

3. The method according to claim 1, further comprising:

setting a separate dispatcher for each hardware thread of said exclusive set of processors to only execute work on each local run queue associated with each said hardware thread of said exclusive set of processors;

draining any tasks waiting on each local run queue associated with each said hardware thread of said exclusive set of processors;

passing each said hardware thread of said exclusive set of processors to an idle process, wherein said idle process searches each local run queue and cedes each said hardware thread of said exclusive set of processors to a hypervisor while each local run queue associated with each hardware thread of said exclusive set of processors remains empty, wherein said hypervisor automatically returns each said hardware thread to said idle process while each local run queue associated with each said hardware thread of said exclusive set of processors remains empty;

applying each separate task of said ST workload to a separate local run queue of each said selected one hardware thread per processor within said exclusive set of processors;

sending an interrupt to direct said hypervisor to return those selected one hardware thread per processor currently ceded to said hypervisor; and

responsive to detecting said remaining hardware threads ceded to said hypervisor, placing each of said remaining hardware threads in a snooze mode, wherein only a particular selection of interrupts awakens each hardware thread placed in snooze mode to return to said idle mode.

4. The method according to claim 1, further comprising:

applying each separate task of said ST workload to a separate local run queue of each selected one hardware thread per processor; and

blocking placement of any other tasks on a remaining selection of local run queues of said remaining idle hardware threads per processor within said exclusive set of processors.

5. The method according to claim 1, further comprising:

concurrently, executing a SMT workload on the plurality of activated hardware threads of the remaining non-exclusive processors.

6. The method according to claim 1, wherein scheduling said ST workload further comprises:

detecting a selection of processors available for inclusion in said exclusive set of processors; and

enabling said ST workload to request construction of said exclusive set of processors with processors designated from among said selection of processors.

7. The method according to claim 1, wherein facilitating construction of an exclusive set of processors further comprises:

receiving an ST workload with a request for said exclusive set of processors solely defined by said number of said plurality of tasks of said ST workload;

detecting a selection of processors available for inclusion in said exclusive set of processors;

triggering a command to create said exclusive set of processors of a same number as said number of said plurality of tasks with processors designated from among said selection of processors; and

attaching said exclusive set of processors to said ST workload.

8. The method according to claim 1, further comprising:

receiving, at a kernel layer of said SMT enabled processing system, an ST workload and a selection of processors marked as exclusive via an application programming interface with an application layer.

9. A simultaneous multi-thread (SMT) enabled processing system, comprising:

a plurality of processors each enabled for simultaneous execution of multiple hardware threads;

a memory for storing a kernel for controlling application of workloads to said plurality of processors;

said kernel for facilitating construction of an exclusive set of processors from among said plurality of processors to handle a plurality of tasks of an single-threaded (ST) workload; and

said kernel for scheduling said ST workload on said exclusive set of processors by selecting only one hardware thread per processor within said exclusive set of processors to handle a separate one of said plurality of tasks of the ST workload while requiring the remaining hardware threads per processor within said exclusive set of processors to idle, such that said ST workload is executed on a multi-threaded processor system enabled for simultaneous execution as if said exclusive set of processors are running in ST mode without deactivating the remaining idle hardware threads per processor within said exclusive set of processors.

10. The system according to claim 9, said kernel further comprising:

means for setting a separate dispatcher for each hardware thread of said exclusive set of processors to only execute work on each local run queue associated with each said hardware thread of said exclusive set of processors;

means for draining any tasks waiting on each local run queue associated with each said hardware thread of said exclusive set of processors;

means, responsive to placing each said hardware thread of said exclusive set of processors in an idle mode without any tasks to perform, for setting each said hardware thread of said exclusive set of processors in a snooze mode, wherein only an interrupt awakens each said hardware thread placed in snooze mode to search an associated local run queue for waiting tasks;

means for applying each separate task of said ST workload to a separate local run queue of each said selected one hardware thread per processor within said exclusive set of processors;

means for sending an interrupt to wake up said selected one hardware thread per processor.

11. The system according to claim 9, said kernel further comprising:

means for setting a separate dispatcher for each hardware thread of said exclusive set of processors to only execute work on each local run queue associated with each said hardware thread of said exclusive set of processors;

means for draining any tasks waiting on each local run queue associated with each said hardware thread of said exclusive set of processors;

means for passing each said hardware thread of said exclusive set of processors to an idle process, wherein said idle process searches each local run queue and cedes each said hardware thread of said exclusive set of processors to a hypervisor while each local run queue associated with each hardware thread of said exclusive set of processors remains empty, wherein said hypervisor automatically returns each said hardware thread to said idle process while each local run queue associated with each said hardware thread of said exclusive set of processors remains empty;

means for applying each separate task of said ST workload to a separate local run queue of each said selected one hardware thread per processor within said exclusive set of processors;

means for sending an interrupt to direct said hypervisor to return those selected one hardware thread per processor currently ceded to said hypervisor; and

means, responsive to detecting said remaining hardware threads ceded to said hypervisor, for placing each of said remaining hardware threads in a snooze mode, wherein only a particular selection of interrupts awakens each hardware thread placed in snooze mode to return to said idle mode.

12. The system according to claim 9, said kernel further comprising:

means for applying each separate task of said ST workload to a separate local run queue of each selected one hardware thread per processor; and

means for blocking placement of any other tasks on a remaining selection of local run queues of said remaining idle hardware threads per processor within said exclusive set of processors.

13. The system according to claim 9, said kernel further comprising:

means for concurrently, executing a SMT workload on the plurality of activated hardware threads of the remaining non-exclusive processors.

14. The system according to claim 9, wherein said kernel for scheduling said ST workload further comprises:

means for detecting a selection of processors available for inclusion in said exclusive set of processors; and

means for enabling said ST workload to request construction of said exclusive set of processors with processors designated from among said selection of processors.

15. The system according to claim 9, wherein said kernel for facilitating construction of an exclusive set of processors further comprises:

means for receiving an ST workload with a request for said exclusive set of processors solely defined by said number of said plurality of tasks of said ST workload;

means for detecting a selection of processors available for inclusion in said exclusive set of processors;

means for triggering a command to create said exclusive set of processors of a same number as said number of said plurality of tasks with processors designated from among said selection of processors; and

means for attaching said exclusive set of processors to said ST workload.

16. The system according to claim 9, said kernel further comprising:

means for receiving, at a kernel layer of said SMT enabled processing system, an ST workload and a selection of processors marked as exclusive via an application programming interface with an application layer.

A program for virtually rendering a consumer image wearing at least one merchandise item, said program embodied in a computer-readable medium, said program comprising computer-executable instructions which cause a computer to perform the steps of;

17. A program for managing a simultaneous multi-threaded (SMT) enabled processor system comprising a plurality of processors each activated to simultaneously execute a plurality of hardware threads, said program embodied in a computer-readable medium, said program comprising computer-executable instructions which cause a computer to perform the steps of:

controlling construction of an exclusive set of processors from among said plurality of processors to handle a plurality of tasks of an single-threaded (ST) workload in said SMT enabled processing system; and

controlling scheduling of said ST workload on said exclusive set of processors by selecting only one hardware thread per processor within said exclusive set of processors to handle a separate one of said plurality of tasks of the ST workload while requiring the remaining hardware threads per processor within said exclusive set of processors to idle, wherein said ST workload is executed on an SMT enabled processor system as if said exclusive set of processors are running in ST mode without deactivating the remaining idle hardware threads per processor within said exclusive set of processors.

18. The program according to claim 17, said program further comprising computer-executable instructions which cause a computer to perform the steps of:

setting a separate dispatcher for each hardware thread of said exclusive set of processors to only execute work on each local run queue associated with each said hardware thread of said exclusive set of processors;

draining any tasks waiting on each local run queue associated with each said hardware thread of said exclusive set of processors;

responsive to placing each said hardware thread of said exclusive set of processors in an idle mode without any tasks to perform, setting each said hardware thread of said exclusive set of processors in a snooze mode, wherein only an interrupt awakens each said hardware thread placed in snooze mode to search an associated local run queue for waiting tasks;

applying each separate task of said ST workload to a separate local run queue of each said selected one hardware thread per processor within said exclusive set of processors;

sending an interrupt to wake up said selected one hardware thread per processor.

19. The program according to claim 17, said program further comprising computer-executable instructions which cause a computer to perform the steps of:

setting a separate dispatcher for each hardware thread of said exclusive set of processors to only execute work on each local run queue associated with each said hardware thread of said exclusive set of processors;

draining any tasks waiting on each local run queue associated with each said hardware thread of said exclusive set of processors;

passing each said hardware thread of said exclusive set of processors to an idle process, wherein said idle process searches each local run queue and cedes each said hardware thread of said exclusive set of processors to a hypervisor while each local run queue associated with each hardware thread of said exclusive set of processors remains empty, wherein said hypervisor automatically returns each said hardware thread to said idle process while each local run queue associated with each said hardware thread of said exclusive set of processors remains empty;

applying each separate task of said ST workload to a separate local run queue of each said selected one hardware thread per processor within said exclusive set of processors;

sending an interrupt to direct said hypervisor to return those selected one hardware thread per processor currently ceded to said hypervisor; and

responsive to detecting said remaining hardware threads ceded to said hypervisor, placing each of said remaining hardware threads in a snooze mode, wherein only a particular selection of interrupts awakens each hardware thread placed in snooze mode to return to said idle mode.

20. The program according to claim 17, said program further comprising computer-executable instructions which cause a computer to perform the steps of:

applying each separate task of said ST workload to a separate local run queue of each selected one hardware thread per processor; and

blocking placement of any other tasks on a remaining selection of local run queues of said remaining idle hardware threads per processor within said exclusive set of processors.