Shielding structures for preventing leakages in high voltage MOS devices

• US 20080001189A1
• Filed: 11/06/2006
• Published: 01/03/2008
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Chi-Hsuen, Hsu, Shun-Liang, Liu, Ruey-Hsin, Jong, Yu-Chang, Hsia, Te-Yin, Lin, Yueh-Chiou
• Granted Patent: US 7,521,741 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.

Claims

1. A semiconductor structure comprising:

a substrate;

a first high-voltage well (HVW) region of a first conductivity type overlying the substrate;

a second HVW region of the first conductivity type overlying the substrate;

a third HVW region overlying the substrate, wherein the third HVW region is of a second conductivity type opposite the first conductivity type, and wherein the third HVW region has at least a portion between the first HVW region and the second HVW region;

an insulation region in the first HVW region, the second HVW region, and the third HVW region;

a gate dielectric over and extending from the first HVW region to the second HVW region;

a gate electrode on the gate dielectric; and

a shielding pattern over the insulation region, wherein the shielding pattern is electrically insulated from the gate electrode, and wherein the gate electrode and the shielding pattern have a spacing of less than about 0.4 μ

m.

2. The semiconductor structure of claim 1, wherein the spacing is less than about 0.25 μ

m.

3. The semiconductor structure of claim 1, wherein the spacing is equal to a minimum spacing defined by design rules.

4. The semiconductor structure of claim 1, wherein the shielding pattern is connected to a voltage substantially lower than a stress voltage applied to the gate electrode.

5. The semiconductor structure of claim 1, wherein the shielding pattern is connected to the substrate.

6. The semiconductor structure of claim 1, wherein a ratio of a length of the shielding pattern to a length of the gate electrode is greater than about 0.2.

7. The semiconductor structure of claim 1 further comprising:

an additional insulation region in the first HVW region, the second HVW region, and the third HVW region, the additional insulation region being on an opposite side of the gate dielectric from the insulation region; and

an additional shielding pattern over the additional insulation region, wherein the additional shielding pattern is electrically insulated from the gate electrode, and wherein the gate electrode and the additional shielding pattern have a spacing of less than about 0.4 μ

m.

8. The semiconductor structure of claim 1, wherein the gate electrode and the shielding pattern are formed of a same material.

9. The semiconductor structure of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

10. A semiconductor structure comprising:

a substrate;

a first high-voltage N-well (HVNW) region overlying the substrate;

a second HVNW region overlying the substrate;

a high-voltage P-well (HVPW) region overlying the substrate, the HVPW region having at least a portion between the first HVNW region and the second HVNW region;

an insulation region in the first HVNW region, the second HVNW region, and the HVPW region;

a gate dielectric over and extending from the first HVNW region to the second HVNW region;

a gate electrode on the gate dielectric; and

a shielding pattern over the insulation region, wherein the shielding pattern is electrically insulated from the gate electrode, and wherein the shielding pattern is connected to a shielding voltage substantially lower than a stress voltage when the stress voltage is applied to the gate electrode.

11. The semiconductor structure of claim 10, wherein the shielding voltage is less than about 50 percent of the stress voltage.

12. The semiconductor structure of claim 11, wherein the shielding pattern is grounded.

13. A semiconductor structure comprising:

a substrate;

a first high-voltage N-well (HVNW) region and a second HVNW region in the substrate, the first and the second HVNW regions being along a first direction;

a high-voltage P-well (HVPW) region in the substrate, the HVPW region having at least a portion between the first HVNW region and the second HVNW region;

a gate dielectric over and extending from the first HVNW region to the second HVNW region;

a gate electrode on the gate dielectric;

an insulation region in the first HVNW region, the second HVNW region and the HVPW region, wherein the insulation region comprises a portion extending from the edge of the gate dielectric in a second direction perpendicular to the first direction; and

a shielding pattern over the insulation region, wherein the shielding pattern is electrically insulated from the gate electrode, and wherein the gate electrode and the shielding pattern have a spacing of less than about 0.4 μ

m.

14. The semiconductor structure of claim 13, wherein the spacing is less than about 0.25 μ

m.

15. The semiconductor structure of claim 13, wherein the gate electrode and the shielding pattern are formed of a same material.

16. The semiconductor structure of claim 13, wherein a ratio of a length of the shielding pattern to a length of the gate electrode is greater than about 0.2.

17. The semiconductor structure of claim 13, wherein the shielding pattern is directly on the insulation region.

18. The semiconductor structure of claim 13 further comprising:

an additional insulation region in the first HVNW region, the second HVNW region, and the HVPW region and on an opposite side of the gate dielectric from the insulation region; and

an additional shielding pattern over the additional insulation region, wherein the additional shielding pattern is electrically insulated from the gate electrode, and wherein the gate electrode and the additional shielding pattern have a spacing of less than about 0.4 μ

m.

19. The semiconductor structure of claim 13, wherein the insulation region is a shallow trench isolation region.

20. The semiconductor structure of claim 13, wherein the insulation region has a depth of less than about 0.5 μ

m.