Non-volatile memory device and method of manufacturing the non-volatile memory device

• US 20080001209A1
• Filed: 04/10/2007
• Published: 01/03/2008
• Est. Priority Date: 06/29/2006
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Eun-Suk, Choe, Jeong-Dong, Park, Kyu-Charn, Lee, Jong-Jin
• Application Number:
  US11/783,548
• Publication Number:
  US 20080001209A1
• Time in Patent Office: Days
• US Class Current: 257/321
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory device may include a substrate having a field region and an active region including a rounded upper edge portion and a flat upper central portion, an effective tunnel oxide layer on the flat upper central portion of the active region, a split floating gate electrode on the effective tunnel oxide layer, the floating gate electrode having a width greater than a width of the effective tunnel oxide layer, a dielectric layer pattern on the floating gate electrode, the dielectric layer pattern including metal oxide, and a control gate electrode on the dielectric layer pattern.

Claims

1. A non-volatile memory device, comprising:

a substrate having a field region and an active region including a rounded upper edge portion and a flat upper central portion;

an effective tunnel oxide layer on the flat upper central portion of the active region;

a split floating gate electrode on the effective tunnel oxide layer, the floating gate electrode having a width greater than a width of the effective tunnel oxide layer;

a dielectric layer pattern on the floating gate electrode, the dielectric layer pattern including metal oxide; and

a control gate electrode on the dielectric layer pattern.

2. The non-volatile memory device as claimed in claim 1, wherein the dielectric layer pattern is a split dielectric layer pattern having a shape corresponding to a shape of the floating gate electrode.

3. The non-volatile memory device as claimed in claim 1, wherein the dielectric layer pattern is a linear dielectric layer pattern extending on the field region beyond the rounded upper edge portion of the active region.

4. The non-volatile memory device as claimed in claim 1, wherein the dielectric layer pattern includes at least one of tantalum oxide (Ta₂O₅), titanium oxide (TiO₂), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), hafnium silicate (HfSi_xO_y), zirconium silicate (ZrSi_xO_y), hafnium nitride silicate (HfSi_xO_yN_z), zirconium nitride silicate (ZrSi_xO_yN_z), aluminum oxide (Al₂O₃), aluminum nitride oxide (Al_xO_yN_z), hafnium aluminate (HfAl_xO_y), yttrium oxide (Y₂O₃), niobium oxide (Nb₂O₅), cesium oxide (CeO₂), indium oxide (InO₃), lanthanum oxide (LaO₂), strontium titanium oxide (SrTiO₃), lead titanium oxide (PbTiO₃), strontium ruthenium oxide (SrRuO₃) and calcium ruthenium oxide (CaRuO₃).

5. The non-volatile memory device as claimed in claim 1, wherein the floating gate electrode includes polysilicon.

6. The non-volatile memory device as claimed in claim 1, wherein the control gate electrode includes a metal nitride layer pattern.

7. The non-volatile memory device as claimed in claim 6, further comprising a polysilicon layer pattern on the metal nitride layer pattern.

8. The non-volatile memory device as claimed in claim 1, wherein the floating gate electrode has a thickness of about 150 Å

to about 300 Å

.

9. A method of manufacturing a non-volatile memory device, comprising:

forming a preliminary gate structure on a substrate, the preliminary gate structure including a preliminary tunnel oxide layer, a preliminary floating gate electrode and a preliminary dielectric layer pattern including metal oxide, which are sequentially stacked;

selectively oxidizing surfaces of the substrate at sides of the preliminary gate structure to form an effective tunnel oxide layer including the preliminary tunnel oxide layer;

forming trench isolation layers in the substrate at the sides of the preliminary gate structure to define a field region and an active region of the substrate;

forming a conductive layer on the preliminary gate structure; and

patterning the preliminary floating gate electrode, the preliminary dielectric layer pattern and the conductive layer to form a floating gate electrode, a dielectric layer pattern and a control gate electrode.

10. The method as claimed in claim 9, wherein the preliminary dielectric layer pattern includes at least one of tantalum oxide (Ta₂O₅), titanium oxide (TiO₂), hafnium oxide (HfO₂), zirconium oxide (ZrO₂), hafnium silicate (HfSi_xO_y), zirconium silicate (ZrSi_xO_y), hafnium nitride silicate (HfSi_xO_yN_z), zirconium nitride silicate (ZrSi_xO_yN_z), aluminum oxide (Al₂O₃), aluminum nitride oxide (Al_xO_yN_z), hafnium aluminate (HfAl_xO_y), yttrium oxide (Y₂O₃), niobium oxide (Nb₂O₅), cesium oxide (CeO₂), indium oxide (InO₃), lanthanum oxide (LaO₂), strontium titanium oxide (SrTiO₃), lead titanium oxide (PbTiO₃), strontium ruthenium oxide (SrRuO₃) and calcium ruthenium oxide (CaRuO₃).

11. The method as claimed in claim 9, wherein selectively oxidizing surfaces of the substrate at sides of the preliminary gate structure comprises selectively oxidizing surfaces of the substrate using a wet oxidation process.

12. The method as claimed in claim 9, further comprising forming a hard mask pattern on the preliminary dielectric layer pattern, the hard mask pattern being used for patterning the preliminary gate structure and including silicon nitride.

13. The method as claimed in claim 12, further comprising forming a spacer including silicon nitride on sidewalls of the preliminary gate structure and the hard mask pattern.

14. The method as claimed in claim 13, wherein forming the trench isolation layer comprises;

etching the substrate using the preliminary gate structure as an etching mask to form an isolation trench;

filling the isolation trench with a preliminary isolation layer;

partially removing the preliminary isolation layer until a sidewall of the preliminary dielectric layer pattern is partially exposed to form the trench isolation layer; and

removing the hard mask pattern to expose an upper face of the preliminary dielectric layer pattern.

15. The method as claimed in claim 14, wherein before forming the preliminary isolation layer, the method comprises oxidizing the spacer on the sidewalls of the preliminary gate structure and the hard mask pattern to convert the silicon nitride in the spacer into oxide.

16. The method as claimed in claim 15, wherein the spacer is oxidized using a radical oxidation process.

17. The method as claimed in claim 9, wherein selectively oxidizing surface of the substrate comprises selectively oxidizing surfaces of the substrate at opposing sides of the preliminary gate structure.

18. A method of manufacturing a non-volatile memory device, comprising:

forming a preliminary gate structure on a substrate, the preliminary gate structure including a preliminary tunnel oxide layer and a preliminary floating gate electrode sequentially stacked;

selectively oxidizing surfaces of the substrate at both sides of the preliminary gate structure to form an effective tunnel oxide layer including the preliminary tunnel oxide layer;

forming trench isolation layers in the substrate at the both sides of the preliminary gate structure to define a field region and an active region of the substrate, the active region having a flat upper central portion on which the effective tunnel oxide layer is positioned;

sequentially forming a dielectric layer including metal oxide and a control gate layer on the preliminary gate structure; and

patterning the preliminary floating gate electrode, the dielectric layer and the control gate layer to form a split floating gate electrode, a dielectric layer pattern and a control gate electrode.

19. The method as claimed in claim 18, further comprising sequentially forming a buffer oxide layer pattern and a hard mask pattern on the preliminary dielectric layer pattern, the buffer oxide layer pattern and hard mask pattern being used for patterning the preliminary gate structure.

20. The method as claimed in claim 19, wherein forming the trench isolation layer comprises;

etching the substrate using the preliminary gate structure as an etching mask to form an isolation trench;

filling the isolation trench with a preliminary isolation layer;

partially removing the preliminary isolation layer to form the trench isolation layer, the trench isolation layer having an upper surface that is positioned on a plane on which an upper surface of the preliminary floating gate electrode is placed; and

removing the hard mask pattern and the buffer oxide layer pattern to expose an upper face of the preliminary floating gate electrode.