TRENCH TRANSISTOR

• US 20080001216A1
• Filed: 06/28/2007
• Published: 01/03/2008
• Est. Priority Date: 06/28/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Krischke, Norbert, Kotz, Dietmar, Peri, Hermann, Lanzerstorfer, Sven
• Granted Patent: US 7,535,055 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench transistor is disclosed. One embodiment has an active zone enclosed by an edge trench, wherein an edge electrode at gate potential is embedded into the edge trench, and the active zone has a mesa structure at least partly adjoining the edge trench. That region of the mesa structure which adjoins the edge trench is at least partly electrically deactivated by virtue of the fact that within this deactivated region a) the mesa structure is covered with a mesa insulation layer, and b) no source zone is provided.

Claims

1. A trench transistor comprising:

an active zone enclosed by an edge trench;

an edge electrode at gate potential embedded into the edge trench; and

a mesa structure in the active zone at least partly adjoining the edge trench;

wherein that region of the mesa structure that adjoins the edge trench is at least partly electrically deactivated by virtue of the fact that within the deactivated region the mesa structure is covered with a mesa insulation layer, and no source zone is provided.

2. A trench transistor of claim 1, wherein the mesa insulation layer is produced together with a field electrode insulation layer, which serves for insulating a field electrode structure embedded into the edge trenches and/or into the gate trenches from the mesa structure, in one process.

3. The trench transistor of claim 1, wherein the mesa insulation layer and the field electrode insulation layer are produced by oxidation of the mesa structure.

4. The trench transistor of claim 1, wherein the mesa structure has a plurality of strip-type mesa zones whose end sides adjoin the edge trench.

5. The trench transistor of claim 4, wherein the mesa insulation layer covers the end sides and also those regions of the longitudinal sides and of the top sides of the mesa zones which adjoin the end sides.

6. The trench transistor of claim 5, wherein no source zones are formed below that region of the mesa insulation layer which covers the top sides of the mesa zones.

7. The trench transistor of claim 5, wherein body zones are formed below that region of the mesa insulation layer which covers the top sides of the mesa zones, the body zones in each case reaching as far as the end sides of the mesa zones.

8. The trench transistor claim 5, wherein the lateral extent of the mesa insulation layer, proceeding from one end side of a mesa zone in the direction of the respective other end side of the mesa zone, lies within a range of between 0.1 μ

m and 2 μ

m.

9. A method for producing a trench transistor, comprising:

providing an active zone enclosed by an edge trench on a semiconductor body;

providing a mesa structure within the active zone and at least partly adjoining the edge trench;

producing an insulation layer covering the mesa structure,

etching back the insulation layer into the edge trench and/or into a gate trench structure pervading/bordering the mesa structure, wherein the residues of the insulation layer that remain in the edge region and in the gate trench structure serve for insulating a field electrode structure that is to be introduced into the trenches from the semiconductor body, and wherein the etching back is effected in such a way that that region of the mesa structure which adjoins the edge trench is at least partly covered by the insulation layer; and

forming body zones and source zones in the mesa structure using the insulation layer as a mask.

10. The method of claim 13, wherein the insulation layer is produced by oxidation of the mesa structure.

11. The method of claim 9, wherein the mesa structure has a plurality of strip-type mesa zones whose end sides adjoin the edge trench.

12. The method of claim 11, wherein the etching back is effected in such a way that the insulation layer, after the etching back, covers the end sides and also those regions of the longitudinal sides and of the top sides of the mesa zones which adjoin the end sides.

13. The method of claim 12, wherein body zones are formed below that region of the insulation layer which covers the top sides of the mesa zones, the body zones in each case reaching as far as the end sides of the mesa zones, by virtue of the fact that dopants of a first conduction type are introduced into the mesa structure using the insulation layer as a mask, and a heat treatment process is subsequently performed, which has the effect that the dopants introduced diffuse as far as the respective end sides.

14. The trench transistor of claim 12, wherein source zones are formed below that region of the insulation layer which covers the top sides of the mesa zones, the source zones not reaching as far as the end sides of the mesa zones, by virtue of the fact that dopants of a second conduction type are introduced into the mesa structure using the insulation layer as a mask.

15. The method of claim 14, wherein the lateral extent of the mesa insulation layer is chosen, and the introduction of the dopants of the second conduction type is effected, such that the lateral distance between the source zones and the end sides lies within a range of between 0.1 μ

m and 2 μ

m.

16. A trench transistor comprising:

an active zone enclosed by an edge trench;

an edge electrode at gate potential embedded into the edge trench;

a mesa structure in the active zone at least partially adjoining the edge trench, and

insulating means covering the mesa structure for deactivating the region of the mesa structure that adjoins the edge trench.

17. The trench transistor of claim 16, wherein no source zone is provided such that the region of the mesa structure that adjoins the edge trench is deactivated.

18. The trench transistor of claim 16, wherein the insulation means comprises a mesa insulation layer.

19. The trench transistor of claim 18, wherein the mesa insulation layer is produced together with a field electrode insulation layer, which serves for insulating a field electrode structure embedded into the edge trenches and/or into the gate trenches from the mesa structure, in one process.

20. The trench transistor of claim 18, wherein the mesa insulation layer and the field electrode insulation layer are produced by oxidation of the mesa structure.