Semiconductor device having superjunction structure and method for manufacturing the same

• US 20080001217A1
• Filed: 06/28/2007
• Published: 01/03/2008
• Est. Priority Date: 07/03/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Kawashima, Yoshiya
• Granted Patent: US 7,649,223 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

An n-type drift region includes an active element region and a peripheral region. A p-type base region is formed at least in the active element region. A trench-type gate electrode is formed in each of the active element region and the peripheral region. An n-type source region formed in the base region. A plurality of p-type column regions is selectively formed separately from one another in each of the active element region and the peripheral region. In a peripheral region, a p-type guard region is formed below the gate electrode. In the active element region, the p-type guard region is not formed below the gate electrode. As a result, it is possible to hold the breakdown voltage in the peripheral region at a higher level than in the active element region while maintaining the low ON resistance due to a superjunction structure and to raise the breakdown voltage performance of the semiconductor device.

Claims

1. A semiconductor device comprising:

a drift region of a first conductivity type including an active element region and a peripheral region formed around said active element region;

a first trench formed in said peripheral region;

a second trench formed in said active element region;

a gate insulating film and a gate electrode formed in each of said first and second trenches;

a base region of a second conductivity type formed at least in said active element region;

a plurality of column regions of said second conductivity type selectively formed separately from one another in each of said active element region and said peripheral region to thereby form a parallel p-n layer that comprises a portion of said drift region and selected ones of said column regions;

a source region of said first conductivity type formed in said base region; and

a guard region of said second conductivity type formed below at least a portion of said first trench closest to said active element region, said guard region being free from being formed below said second trench.

2. The semiconductor device according to claim 1, wherein said guard region is formed below an entire area of said first trench.

3. The semiconductor device according to claim 1, further comprises a field electrode formed over said peripheral region and electrically connected to said gate electrode, said field electrode being formed without covering at least one of said column regions formed in said peripheral region, said at least one of said column regions being closest to said active element region.

4. The semiconductor device according to claim 3, wherein said at least one of said column regions formed in said peripheral region is formed with a depth of not less than a depth D of said plurality of column regions formed in said active element region, and said field electrode is free from being formed at least just above said column region having a depth of not less than said depth D.

5. The semiconductor device according to claim 1, wherein all of said column regions formed in said peripheral region are formed with a depth of not less than said depth D of said plurality of column regions formed in said active element region.

6. The semiconductor device according to claim 4, wherein said column region having a depth of not less than said depth D in said peripheral region is formed outward from an end portion closest to said active element region of said field electrode.

7. The semiconductor device according to claim 4, wherein the semiconductor device further comprises a connecting electrode that is formed in said peripheral region and is connected to said gate electrode and said field electrode, and said column region having a depth of not less than said depth D in said peripheral region is located outward from a connecting portion between said connecting electrode and said field electrode.

8. The semiconductor device according to claim 3, wherein said field electrode has an opening that is formed over at least one of said column regions formed in said peripheral region.

9. The semiconductor device according to claim 1, further comprises a guard insulating film that is formed at a bottom of said first trench, said guard insulating film having a film thickness larger than said gate insulating film formed in said second trench.

10. The semiconductor device according to claim 1, wherein said first trench is formed so as to surround a circumference of each of said column regions as viewed on a horizontal plane also in said peripheral region.

11. The semiconductor device according to claim 3, wherein said field electrode is formed outward from all of said column region.

12. The semiconductor device according to claim 3, wherein said field electrode is formed over at least one of said column regions.

13. The semiconductor device according to claim 1, wherein all of said column regions formed in said active element region and said peripheral region have an impurity profile that is substantially equal.

14. The semiconductor device according to claim 1, wherein the shape of said portion of said drift region forming said parallel p-n layer is in the form of a mesh as viewed on a horizontal plane.

15. The semiconductor device according to claim 1, wherein the shape of said portion of said drift region forming said parallel p-n layer is in the form of a plurality of stripes as viewed on a horizontal plane.

16. The semiconductor device according to claim 1, wherein said plurality of column regions are arranged in the form of a plurality of islands and have a plane arrangement in the form of an orthorhombic lattice.

17. The semiconductor device according to claim 1, wherein the semiconductor device further comprises a drain region of said first conductivity type formed below said drift region and said column region is formed with a depth that is free from reaching said drain region at least in said active element region.

18. A method for manufacturing a semiconductor device, comprising:

forming a drift region of a first conductivity type including an active element region and a peripheral region formed around said active element region;

forming a first trench in said peripheral region;

forming a guard region by introducing an impurity of a second conduction type into a bottom of said first trench;

forming a second trench in said active element region;

forming a gate insulating film in each of said first and second trenches;

forming a gate electrode in each of said first and second trenches and forming a field electrode electrically connected to said gate electrode over said peripheral region;

forming a plurality of column regions of said second conductivity type in each of said active element region and said peripheral region,

forming a base region of said second conductivity type at least in said active element region; and

forming a source region of said first conductivity type in said base region,

wherein said field electrode is formed without covering at least one of said column regions formed in said peripheral region, said at least one of said column regions being closest to said active element region.

19. The method for manufacturing a semiconductor device, according to claim 18, wherein said forming said gate insulating film further includes forming a guard insulating film that is thicker than said gate insulating film formed in said second trench at a bottom of said first trench.