Method of forming a transistor having gate protection and transistor formed according to the method

• US 20080001236A1
• Filed: 06/28/2006
• Published: 01/03/2008
• Est. Priority Date: 06/28/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Change, Peter L.D.
• Granted Patent: US 7,544,594 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A microelectronic device and a method of forming same. The method comprises: a transistor gate; a first spacer and a second spacer respectively adjacent a first side and a second side of the gate; a diffusion layer supra-adjacent the gate; contact regions super-adjacent the diffusion layer and adjacent the first spacer and the second spacer; a protective cap super-adjacent the gate and between the contact regions, the protective cap being adapted to protect the device from shorts between the gate and the contact regions.

Claims

1. A microelectronic device comprising:

a transistor gate;

a first spacer and a second spacer respectively adjacent a first side and a second side of the gate;

a diffusion layer supra-adjacent the gate;

contact regions super-adjacent the diffusion layer and adjacent the first spacer and the second spacer;

a protective cap super-adjacent the gate and between the contact regions, the protective cap being adapted to protect the device from shorts between the gate and the contact regions.

2. The device of claim 1, wherein the protective cap comprises silicon nitride.

3. The device of claim 1, wherein the protective cap is disposed substantially within outer lateral boundaries of the first and second spacers.

4. The device of claim 3, wherein the protective cap extends substantially to the outer lateral boundaries of the first and second spacers and is super-adjacent the first and second spacers.

5. The device of claim 3, wherein the protective cap is disposed substantially within outer lateral boundaries of the gate.

6. The device of claim 1, wherein each of the contact regions includes a self-aligned contact region super-adjacent the diffusion layer, and a metal one region super-adjacent the self-aligned contact region, the self-aligned contact region and the metal one region defining a line of demarcation therebetween.

7. The device of claim 1, wherein each of the contact regions includes a continuous metal one layer super-adjacent the diffusion layer.

8. A method of making a microelectronic device comprising:

providing a transistor structure including a transistor gate, a diffusion layer supra-adjacent the gate, a first spacer adjacent one side of the gate and a second spacer adjacent another side of the gate;

providing a protective cap super-adjacent the gate;

providing contact regions super-adjacent the diffusion layer, the contact regions including a first contact region adjacent the first spacer and one side of the protective cap, and a second contact region adjacent the second spacer and an opposite side of the protective cap.

9. The method of claim 8, wherein the protective cap comprises silicon nitride.

10. The method of claim 8, wherein the transistor structure further comprises a first ILD layer encompassing the gate, the first spacer and the second spacer, and wherein providing a protective cap comprises:

providing a sacrificial cap onto the gate;

providing a second ILD layer encompassing the sacrificial cap super-adjacent the first ILD layer;

defining a protective cap recess by removing the sacrificial cap from the second ILD layer;

forming a protective cap body by providing a protective material in the protective cap recess;

removing portions of the second ILD layer to provide the protective cap.

11. The method of claim 10, wherein the sacrificial cap comprises a metal material, and wherein providing the sacrificial cap comprises selectively depositing sacrificial cap material by electrolessly plating the sacrificial cap material onto the gate.

12. The method of claim 10, wherein providing the sacrificial cap comprises selectively depositing sacrificial cap material by carbon nano-tube depositing the sacrificial cap material onto the gate.

13. The method of claim 8, wherein the protective cap is disposed substantially within outer lateral boundaries of the first and second spacers.

14. The method of claim 13, wherein the protective cap extends substantially to the outer lateral boundaries of the first and second spacers and is super-adjacent the first and second spacers.

15. The method of claim 13, wherein the protective cap is disposed substantially within outer lateral boundaries of the gate.

16. The method of claim 10, wherein removing comprises removing the sacrificial cap to define an intermediate recess, defining the protective cap recess further comprising removing portions of walls of the intermediate recess.

17. The method of claim 10, wherein providing a sacrificial cap comprises selectively depositing sacrificial cap material onto the gate to form a sacrificial central body, and providing sacrificial spacers on each side of the sacrificial central body to form the sacrificial cap.

18. The method of claim 17, wherein providing sacrificial spacers comprises:

providing a layer of sacrificial material to encompass the sacrificial central body, and anisotropically etching the layer of sacrificial material to obtain the sacrificial spacers.

19. The method of claim 10, wherein the sacrificial cap comprises a metal.

20. The method of claim 8, wherein the protective cap comprises silicon nitride.

21. The method of claim 10, wherein removing the sacrificial cap comprises etching.

22. The method of claim 10, wherein removing portions of the second ILD layer comprises etching.

23. The method of claim 8, wherein providing contact regions includes:

providing self-aligned contact regions super-adjacent the diffusion layer and including a first self-aligned contact region adjacent the first spacer and a second self-aligned contact region adjacent the second spacer; and

providing metal one portions super-adjacent respective ones of the self-aligned contact regions.

24. The method of claim 23, wherein providing self-aligned contact regions comprises:

patterning a photoresist onto the second ILD layer;

etching the first ILD layer and the second ILD layer to the diffusion layer to define self-aligned contact recesses encompassing the gate, the first spacer and the second spacer;

depositing contact metal within the self-aligned contact recesses to define the self-aligned contact regions.

25. The method of claim 23, wherein providing metal one portions comprises:

depositing a third ILD layer onto the self-aligned contact regions;

patterning a photoresist onto the third ILD layer;

etching the third ILD layer to the self-aligned contact regions to define metal line recesses above the self-aligned contact regions;

providing metal one portions within respective ones of the metal one portions recesses to define the metal one portions.

26. The method of claim 8, wherein providing contact regions includes directly patterning metal one portions super-adjacent the diffusion layer.

27. The method of claim 26, wherein directly patterning includes:

depositing a third ILD layer onto the second ILD layer;

patterning a photoresist onto the third ILD layer;

etching the first ILD layer, the second ILD layer and the third ILD layer to the diffusion layer to define metal line recesses encompassing the gate, the first spacer, the second spacer and the protective cap;

depositing contact metal within the metal line recesses to define the contact regions.

28. A system comprising:

a microelectronic device comprising;

a transistor gate;

a first spacer and a second spacer respectively adjacent a first side and a second side of the gate;

a diffusion layer supra-adjacent the gate;

contact regions super-adjacent the diffusion layer and including a first contact region adjacent the first spacer and a second contact region adjacent the second spacer;

a protective cap super-adjacent the gate and adjacent the first contact region and the second contact region, the protective cap being adapted to protect the device from shorts between the gate and the contact regions; and

a graphics processor coupled to the module.

29. The system of claim 28, wherein the protective cap comprises silicon nitride.

30. The system of claim 28, wherein the protective cap is disposed substantially within outer lateral boundaries of the first and second spacers.