Semiconductor device having nitrided high-k gate dielectric and metal gate electrode and methods of forming same

• US 20080001237A1
• Filed: 06/29/2006
• Published: 01/03/2008
• Est. Priority Date: 06/29/2006
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Peng-Fu, Tao, Hun-Jan, Hou, Yong-Tian, Ying, Jin, Yen, Fong-Yu, Chang, Vincent S.
• Application Number:
  US11/478,476
• Publication Number:
  US 20080001237A1
• Time in Patent Office: Days
• US Class Current: 257/411
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Disclosed is a semiconductor device having a substrate, an interfacial layer formed on said substrate, a nitrogen-containing high dielectric constant (high-k) layer formed on said interfacial layer, and a metal electrode on said nitrogen-containing high-k layer. Also disclosed is a method of forming a transistor including forming on a substrate an interfacial layer comprising silicon and oxygen, depositing on the interfacial layer a high-k dielectric material, nitriding the high-k dielectric material, depositing a metal layer on the high-k dielectric material, and patterning the metal layer, the high-k dielectric material, and the interfacial layer to form a gate stack.

Claims

1. A semiconductor device comprising:

a substrate;

a substantially nitrogen-free interfacial layer on said substrate;

a nitrogen-containing high dielectric constant (high-k) layer directly on said interfacial layer; and

a metal electrode on said nitrogen-containing high-k layer.

2. The semiconductor device of claim 1 further comprising:

a first source/drain region formed in said substrate and substantially aligned with a first sidewall of said metal electrode; and

a second source/drain region formed in said substrate and substantially aligned with a second sidewall of said metal electrode.

3. The semiconductor device of claim 1 wherein said nitrogen-containing high-k layer is a metal oxide or a metal silicate containing at least one material selected from the group consisting of hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, dysprosium, scandium, and combinations thereof.

4. The semiconductor device of claim 1 wherein said nitrogen-containing high-k layer comprises a material selected from the group consisting essentially of HfO2 and HfSiO, and has a silicon atomic ratio of between about ten percent and about ninety percent.

5. The semiconductor device of claim 1 wherein said nitrogen-containing high-k layer has a nitrogen atomic ration of between about five percent and about thirty percent.

6. The semiconductor device of claim 1 wherein said nitrogen-containing high-k layer has a thickness of between about 1 nm and about 10 nm and wherein said metal electrode has a thickness of between about 1 nm and about 30 nm.

7. The semiconductor device of claim 1 wherein said nitrogen-containing high-k layer is substantially amorphous.

8. The semiconductor device of claim 1 wherein said metal electrode is a gate electrode and wherein said gate electrode comprises a material selected from the group consisting essentially of tantalum, titanium, hafnium, ruthenium, molybdenum, tungsten, carbon, nitrogen, oxygen, and combinations thereof.

9. The semiconductor device of claim 1 wherein said interfacial layer comprises a material selected from the group consisting essentially of oxygen, nitrogen, silicon, hafnium, aluminum, zirconium, titanium, tantalum, lanthanum, dysprosium, scandium, and combinations thereof.

10. The semiconductor device of claim 1 further comprising:

a polysilicon electrode overlying said metal electrode.

11. The semiconductor device of claim 10 wherein said polysilicon electrode has a thickness of between about 30 nm and about 200 nm.

12. A semiconductor device comprising:

a semiconductor substrate;

a substantially nitrogen-free interfacial layer on said semiconductor substrate;

a gate dielectric on said interface layer, said gate dielectric comprising a nitrogen-containing material having a high dielectric constant;

a metal gate electrode on said gate dielectric;

a non-nitrogen-containing layer on said gate dielectric;

a first source/drain region in said substrate, wherein a portion of said first source/drain region underlies a first portion of said gate dielectric and gate electrode; and

a second source/drain region in said substrate, wherein a portion of said second source/drain region underlies a second portion of said gate dielectric and gate electrode.

13. The semiconductor device of claim 12 further comprising:

a contact formed in an opening in said non-nitrogen-containing layer and electrically coupling said metal gate electrode to another transistor formed on said substrate.

14. The semiconductor device of claim 12 wherein said interfacial layer comprises a material selected from the group consisting essentially of oxygen, nitrogen, silicon, hafnium, aluminum, zirconium, titanium, tantalum, dysprosium, scandium, and combinations thereof.

15. The semiconductor device of claim 12 wherein said gate dielectric comprises a material selected from the group consisting essentially of a metal oxide or a metal silicate containing at least one material selected from the group consisting of hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, dysprosium, scandium, and combinations thereof.

16. The semiconductor device of claim 12 wherein said gate dielectric comprises a material selected from the group consisting essentially of HfO2 and HfSiO, and has a silicon atomic ratio of between about ten percent and about ninety percent.

17. The semiconductor device of claim 12 wherein said gate dielectric has a thickness of about 1 nm and about 10 nm and wherein said metal electrode has a thickness of between about 1 nm and about 30 nm.

18. The semiconductor device of claim 12 wherein said gate dielectric has a nitrogen atomic ration of between about five percent and about thirty percent.

19. An integrated circuit comprising:

a silicon substrate;

a transistor formed at least partially on said substrate, and including a source region;

a drain region;

a channel region defined between said source region and said drain region, said channel region having a nominal length of about or less than about 40 nm;

an interfacial layer overlying the channel region;

a nitrogen-containing high-k gate dielectric overlying the interfacial layer; and

a metal gate electrode overlying the gate dielectric;

an etch stop layer overlying the metal gate electrode;

an inter-layer dielectric over the etch stop layer;

a conductor in said etch stop layer and said inter-layer dielectric, said conductor substantially aligned with said gate electrode; and

an interconnect layer overlying the inter-layer dielectric and electrically contacting the conductor.

20. The integrated circuit of claim 19 wherein said substrate comprises silicon.

21. The integrated circuit of claim 19 wherein said gate dielectric comprises a material selected from the group consisting essentially of HfO2 and HfSiO.

22. The integrated circuit of claim 19 wherein said gate electrode comprises a material selected from the group consisting essentially of tantalum, titanium, hafnium, ruthenium, molybdenum, nitrogen, carbon, and combinations thereof.

23. The semiconductor device of claim 19 further comprising a polysilicon electrode overlying said metal electrode.

24. The semiconductor device of claim 19 wherein said nitrogen containing gate dielectric has a nitrogen atomic ratio of from about five percent to about thirty percent.