Gate driver topology for maximum load efficiency

• US 20080001553A1
• Filed: 06/30/2006
• Published: 01/03/2008
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Qiu, Weihong, Laur, Steven, Abou-Hamze, Rami, Dowlat, Ben
• Granted Patent: US 7,615,940 B2
• Time in Patent Office: Days
• US Class Current: 315/307
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A circuit comprises a first input for receiving a supply voltage and a second input for receiving a sensed current signal from an output of a DC to DC converter. The circuit also includes an output voltage for providing an adjustable drive voltage to a drive circuit. The circuit additionally includes circuitry for adjusting the drive voltage responsive to supply voltage and the sensed current signal.

Claims

1. A DC to DC converter circuit, comprising:

a power stage for generating a DC voltage responsive to drive signals;

a driver circuit for generating the drive signals for power transistors in the power stage responsive to an adjustable drive voltage and drive control signals;

a controller for generating the drive control signals to the driver circuit responsive to a sensed current signal;

a current sensor for generating the sensed current signal responsive to a sensed current in the power stage;

an adaptive drive voltage supply responsive to a voltage supply and the sensed current signal for generating the adjustable drive voltage.

2. The DC to DC converter circuit of claim 1, wherein the current sensor senses a load current of the power stage.

3. The DC to DC converter circuit of claim 2, wherein the adaptive drive voltage supply varies the adjustable drive voltage responsive to the sensed load current to maximize the load efficiency of the DC to DC converter circuit.

4. The DC to DC converter circuit of claim 1, wherein the adaptive drive voltage supply is further responsive to a switching frequency of the power transistors in the power stage.

5. The DC to DC converter circuit of the claim 1, wherein the adaptive drive voltage supply comprises a linear voltage regulator responsive to the voltage supply and the sensed current signal to linearly adjust the adjustable drive voltage between a first voltage responsive to a first sensed current signal and a second voltage responsive to a second sensed current signal.

6. The DC to DC converter circuit of claim 1, wherein the adaptive drive voltage supply comprises a switching voltage regulator responsive to the voltage supply and the sensed current signal to adjust the adjustable drive voltage.

7. The DC to DC converter circuit of claim 1, wherein the adaptive drive voltage supply comprises a plurality of adaptive drive voltage supplies, each of the plurality of adaptive drive voltage supplies providing a different adjustable drive voltage for a portion of the power transistors of the power stage.

8. The DC to DC converter circuit of claim 1, wherein the adaptive drive voltage supply adjusts the adjustable drive voltage responsive to a digital control signal.

9. A circuit comprising:

a first input for receiving a supply voltage;

a second input for receiving a sensed current signal from an output of a DC to DC converter;

an output for providing an adjustable drive voltage to a drive circuit of the DC to DC converter;

first circuitry for adjusting the drive voltage responsive to the supply voltage and the sensed current signal.

10. The circuit of claim 9, wherein the sensed current comprises a load current of the DC to DC converter.

11. The circuit of claim 10, wherein the first circuitry varies the adjustable drive voltage responsive to the sensed load current to maximize the load efficiency of the DC to DC converter circuit.

12. The circuit of claim 9, wherein the first circuitry is further responsive to a switching frequency of power transistors in a power stage.

14. The circuit of claim 9, wherein the first circuitry comprises a switching voltage regulator responsive to the voltage supply and the sensed current signal to adjust the adjustable drive voltage.

16. The circuit of claim 9, further including digital control circuitry for generating a control signal to the first circuitry to adjust the adjustable drive voltage.

13. A circuit comprising:

a first input for recieving a supply voltage;

a secong input for receiving a sensed current signal from an output of a DC to DC converter;

an output for providing an adjustable drive voltage to a drive circuit of the DC to DC converter;

first circuitry for adjusting the drive voltage responsive to the supply voltage and the sensed current signal, wherein the first circuitry comprises a linear voltage regulator responsive to the voltage supply and the sensed current signal to linearly adjust the adjustable drive voltage between a first voltage responsive to a first sensed current signal and a second voltage responsive to a second sensed current signal.

15. A circuit comprising:

a first input for receiving a supply voltage;

a second input for receiving a sensed current signal from an output of a DC to DC converter;

an output for providing an adjustable drive voltage to a drive circuit of the DC to DC converter;

first circuitry for adjusting the drive voltage responsive to the supply voltage and the sensed current signal, wherein the first circuitry comprises a plurality of adaptive drive voltage supplies, each of the plurality of adaptive drive voltage supplies providing a different adjustable drive voltage for a portion of power transistors of a power stage.

17. A method for maximizing a load efficiency of a switched power supply, comprising the steps of:

receiving a supply voltage;

receiving a sensed current signal from an output of the switched power supply; and

providing an adjustable drive voltage to a drive circuit of the switched power supply responsive to the supply voltage and the sensed current signal.

18. The method of claim 17, wherein the sensed current comprises a load current of the switched power supply.

19. The method of claim 18, wherein the step of providing further comprises the step of varying the adjustable drive voltage responsive to the sensed load current to maximize the load efficiency of the switched power supply.

20. The method of claim 17, wherein the step of providing further comprises the step of providing an adjustable drive voltage to a drive circuit of the switched power supply responsive to a switching frequency of the power transistors in the switched power supply, the supply voltage and the sensed current signal.

23. The method of claim 17, wherein the step of providing further comprises:

generating a digital control signal; and

adjusting the adjustable drive voltage responsive to the digital control signal.

21. A method for maximizing a load efficiency of a switched power supply, comprising the steps of:

receiving a supply voltage;

receiving a sensed current signal from an output of the switched power supply; and

providing an adjustable drive voltage to a drive circuit of the switched power supply responsive to the supply voltage and the sensed current signal, wherein the step of providing further comprises the step of linearly adjusting the adjustable drive voltage between a first voltage responsive to a first sensed current signal and a second voltage responsive to a second sensed current signal.

22. A method for maximizing a load efficiency of a switched power supply, comprising the steps of:

receiving a supply voltage;

receiving a sensed current signal from an output of the switched power supply; and

providing an adjustable drive voltage to a drive circuit of the switched power supply responsive to the supply voltage and the sensed current signal, wherein the step of providing further comprises the step of generating a plurality of adaptive drive voltage supplies, each of the plurality of adaptive drive voltage supplies providing a different adjustable drive voltage for a portion of power transistors of the switched power supply.