PHASE SHIFTER

• US 20080001645A1
• Filed: 06/26/2007
• Published: 01/03/2008
• Est. Priority Date: 06/29/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: KUROKI, Reiko
• Granted Patent: US 7,791,390 B2
• Time in Patent Office: Days
• US Class Current: 327/231
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 2005/00286 Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used

Abstract

A phase shifter according to an embodiment of the present invention includes: an AC component amplifying unit; and a dividing circuit. The AC component amplifying unit has positive gain slope characteristics and deforms a waveform of an input differential clock signal to output the deformed differential clock signal. The dividing circuit includes a T-flipflop having two D latches connected in series and receives the deformed differential clock signal defoemed by the AC component amplifying unit to generate at least two output signals having a phase difference of 90 degrees with a frequency of ½ of the deformed differential clock signal.

Claims

1. A phase shifter, comprising:

an AC component amplifying unit having positive gain slope characteristics and deforming a waveform of an input differential clock signal to output the deformed differential clock signal; and

a dividing circuit including a T-flipflop having two D latches connected in series and receiving the deformed differential clock signal deformed by the AC component amplifying unit to generate at least two output signals having a phase difference of 90 degrees with a frequency of ½

of the deformed differential clock signal.

2. The phase shifter according to claim 1, wherein the AC component amplifying unit and the dividing circuit are differential circuit.

3. The phase shifter according to claim 1, wherein the AC component amplifying unit applies a gain to the differential clock signal due to such gain slope characteristics that a gain increases along with an increase in frequency in at least one frequency range, the frequency range including a frequency of the differential clock signal.

4. The phase shifter according to claim 1, wherein the AC component amplifying unit deforms the waveform of the differential clock signal such that an attenuation quantity of a signal amplitude in a period with a long time length of the differential clock signal is larger than an attenuation quantity of a signal amplitude in a period with a short time length of the differential clock signal.

5. The phase shifter according to claim 1, wherein the AC component amplifying unit applies a gain to the differential clock signal owing to such gain slope characteristics that a gain increases along with an increase in frequency in a frequency range from ½

of the frequency of the differential clock signal to the frequency of the clock signal.

6. The phase shifter according to claim 1, further comprising:

a detecting unit detecting a phase difference between the two output signals and outputting a control signal corresponding to the detected phase difference; and

a variable capacitor connected to an output line of at least one of the two output signals and capable of changing a capacitance in accordance with the control signal.

7. The phase shifter according to claim 1, further comprising:

a detecting unit detecting a phase difference between the two output signals and outputting a control signal corresponding to the detected phase difference,

wherein gain slope characteristics of the AC component amplifying unit can be changed in accordance with the control signal.

8. The phase shifter according to claim 1, wherein the differential clock signal input to the AC component amplifying unit has a duty ratio differing from 50%.

9. The phase shifter according to claim 1, wherein the AC component amplifying unit is a low-pass filter.

10. The phase shifter according to claim 3, wherein the AC component amplifying unit has gain slope characteristics of FIG. 6B.

11. A method of generating output signals 90 degrees out of phase with each other, comprising:

deforming a waveform of an input differential clock signal to output the deformed differential clock signal such that an attenuation quantity of a signal amplitude in a period with a long time length of the input differential clock signal is larger than an attenuation quantity of a signal amplitude in a period with a short time length of the input differential clock signal; and

dividing a frequency of the deformed differential to generate at least two output signals having a phase difference of 90 degrees.

12. The method according to claim 11, wherein the input differential clock signal has a duty ratio differing from 50%.