Saturation Detector and Warning Circuit Including Clamp

• US 20080001666A1
• Filed: 06/15/2007
• Published: 01/03/2008
• Est. Priority Date: 06/15/2006
• Status: Active Grant

• Current Assignee: Thomas Szepesi
• Original Assignee: Thomas Szepesi
• Inventors: Szepesi, Thomas
• Granted Patent: US 7,489,199 B2
• Time in Patent Office: Days
• US Class Current: 330/255
• CPC Class Codes: H03F 3/343 with semiconductor devices only

Abstract

A saturation detection and warning circuit having an adaptive threshold voltage is disclosed. The disclosed circuit can also be used to detect the impending drop out of the low drop out linear voltage regulator. A clamp circuit that clamps the amplifier'"'"'s output voltage at a voltage that is separated from the adaptive threshold of the saturation detector and warning circuit by a controlled offset voltage is also disclosed.

Claims

1. A saturation detection and warning circuit to detect the impending saturation of an amplifier, the amplifier having a supply voltage, having inverting and non-inverting input terminals, the amplifier including at least one output transistor providing an output current and an output voltage on an output terminal, having an amplifier front end circuitry connected to the input terminals and controlling the output current of the output transistor,

the saturation detection and warning circuit comprising:

a threshold voltage that tracks changes in process, temperature, supply voltage and output current thereby maximizing the usable output signal range of the amplifier.

2. The saturation detection and warning circuit of claim 1 comprising:

a current mirror transistor having a current that matches the output current of the output transistor with a substantially fixed ratio,

a replica transistor having a current that tracks the output current of the output transistor, the replica transistor having a drain-source voltage that generates the threshold voltage; and

biasing circuitry that biases the replica transistor to set the drain source voltage of the replica transistor to the desired threshold voltage.

3. The saturation detection and warning circuit of claim 2 where the current mirror transistor and replica transistor are implemented with a single transistor.

4. The saturation detection and warning circuit of claim 2 further comprising:

a comparator to compare a Vds drain source voltage of the output transistor and the threshold voltage and to generate a warning signal if the Vds falls below the threshold voltage.

5. The circuit of claim 4, wherein the comparator includes controlled hysteresis.

6. The saturation detection and warning circuit of claim 2 where the threshold voltage is a substantially fixed fraction of a Vdssat voltage of the output transistor, where Vdssat is a drain source voltage of the output transistor at a border of its saturated operating region.

7. The saturation detection and warning circuit of claim 2 where the threshold voltage is a substantially fixed multiple of a minimum drain source voltage of the output transistor, Vdsmin, that can be attained with a given supply voltage and the amplifier front end circuit driving the supply voltage on a control terminal of the output transistor to its maximum absolute value.

8. The circuit of claim 1, further comprising:

a clamp circuit to clamp the output voltage of the amplifier at a controlled level between the threshold voltage and a maximum output voltage the amplifier can provide, that tracks the threshold voltage with an offset.

9. The circuit of claim 8, wherein the offset is substantially fixed.

10. The circuit of claim 8 including a transconductance amplifier with a nonlinear gain having

an inverting and a non-inverting input terminals, one connected to the threshold voltage the other connected to the output terminal of the amplifier,

a controlled offset voltage,

a clamp output terminal generating a clamp current that is dependent of the voltage difference between its two input terminals,

the clamp output terminal being connected to an inverting input terminal of the amplifier.

11. The circuit of claim 10, further comprising:

a comparator to compare a Vds drain source voltage of the output transistor and the threshold voltage and to generate a warning signal if the Vds falls below the threshold voltage, where the clamp circuit and the comparator circuit share significant circuitry to minimize die size and cost.

12. A drop out detection and warning circuit to detect the impending drop-out of a low drop-out linear voltage regulator (LDO) the LDO comprising an input voltage and an output voltage and output current, an error amplifier having two input terminals, one monitoring the output voltage, the other connected to a reference voltage, a pass transistor controlled by the error amplifier,

the drop out detection and warning circuit comparing a drain source voltage of the pass transistor with a threshold voltage that tracks changes in process, temperature, supply voltage and output current, the drop-out detection and warning circuit having an output

terminal that signals that the LDO is close to or about to drop out.

13. The drop out detection and warning circuit of claim 12, comprising:

a current mirror transistor having a current that matches a current of the pass transistor with a substantially fixed ratio;

a replica transistor having a current that tracks the current of the pass transistor, the replica transistor having a drain-source voltage that generates the threshold voltage, and

circuitry that biases the replica transistor to set the drain source voltage of the replica transistor to a desired threshold voltage.

14. The saturation detection and warning circuit of claim 13 where the current mirror transistor and replica transistor are implemented with a single transistor.

15. The drop out detection and warning circuit of claim 13 further comprising:

a comparator to compare a Vds drain source voltage of the pass transistor and the threshold voltage, the comparator to generate a warning signal if the Vds falls below the threshold voltage.

16. The circuit of claim 15, wherein the comparator includes a controlled hysteresis.

17. The drop out detection and warning circuit of claim 13 where the threshold voltage is a substantially fixed fraction of a Vdssat voltage of the pass transistor, the Vdssat voltage being the drain source voltage of the output transistor at the border of its saturated operating region.

18. The drop out detection and warning circuit of claim 13 where the threshold voltage is a substantially fixed multiple of a minimum drain source voltage of the pass transistor, Vdsmin, that can be attained with a given input voltage and an error amplifier driving a voltage on a control terminal of the output transistor to its maximum absolute value.