RFID tag user memory indication

• US 20080001723A1
• Filed: 06/16/2006
• Published: 01/03/2008
• Est. Priority Date: 06/16/2006
• Status: Active Grant

• Current Assignee: Symbol Technologies, LLC (Zebra Technologies Corporation)
• Original Assignee: Symbol Technologies, Inc. (Zebra Technologies Corporation)
• Inventors: Schuessler, Frederick
• Granted Patent: US 7,663,486 B2
• Time in Patent Office: Days
• US Class Current: 340/10.51
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: H04W 88/02 Terminal devices

Abstract

A system and method in a radio frequency identification (RFID) tag for writing and erasing user memory. A write command is received at the tag to write data into user memory of the tag. Based on receipt of the write command, a user memory flag in a first memory bank of the tag is set, and the data is written into a second memory bank of the tag. An erase command is received at the tag to erase data stored in the user memory of the tag. Based on receipt of the command to erase, the user memory flag in the first memory bank is cleared, and data stored in the second memory bank is erased.

Claims

1. A method for writing data into user memory of a radio frequency identification (RFID) tag, comprising:

receiving at the tag a write command to write data into user memory of the tag;

based on receipt of the write command, performing the steps of;

setting a user memory flag in a first memory bank of the tag; and

writing the data into a second memory bank of the tag.

2. The method of claim 1, wherein the tag is a Gen 2 tag, wherein the first memory bank is an Electronic Product Code (EPC) memory bank, wherein said setting step comprises setting bit 15 hex of the EPC memory bank.

3. The method of claim 1, wherein said receiving step comprises:

receiving a write command that specifies a write of the data into the second memory bank and a set of a bit of the first memory bank that represents the user memory flag.

4. The method of claim 3, wherein the write command further specifies a write of additional data into at least one of a third memory bank or a fourth memory bank of the tag, wherein said writing step comprises:

writing the additional data into at least one of the third memory bank or fourth memory bank.

5. The method of claim 3, wherein the write command further specifies a write of additional data into the first memory bank, wherein said writing step comprises:

writing the additional data into the first memory bank.

6. The method of claim 1, wherein the write command includes the data for user memory, wherein receipt of the data for user memory causes logic of the tag to perform the setting step.

7. The method of claim 6, wherein the logic performs the setting step prior to the writing step being performed.

8. The method of claim 6, wherein the logic performs the setting step after the writing step is performed.

9. The method of claim 1, further comprising:

determining whether the second memory bank stores no data prior to the writing step;

wherein said setting step comprises;

setting the user memory flag in the first memory bank if it is determined that the second memory bank stores no data prior to the writing step.

10. The method of claim 1, further comprising:

receiving at the tag a command to erase data stored in the user memory of the tag;

based on receipt of the command to erase, performing the steps of;

clearing the user memory flag in the first memory bank; and

erasing data stored in the second memory bank.

11. The method of claim 1, further comprising:

receiving at the tag a command to erase data stored in the user memory of the tag;

based on receipt of the command to erase, performing the steps of;

determining whether the second memory bank will store no data after execution of the command to erase;

clearing the user memory flag in the first memory bank if it is determined that the second memory bank will store no data after execution of the command to erase; and

erasing data stored in the second memory bank specified in the command to erase.

12. The method of claim 1, further comprising:

performing a cyclic redundancy check (CRC) of bits stored in the first memory bank to account for the setting of the user memory flag.

13. The method of claim 10, further comprising:

performing a cyclic redundancy check (CRC) of bits stored in the first memory bank to account for the clearing of the user memory flag.

14. A radio frequency identification (RFID) tag, comprising:

means for receiving at the tag a write command to write data into user memory of the tag;

means for setting a user memory flag in a first memory bank of the tag in response to receiving the write command; and

means for writing the data into a second memory bank of the tag in response to receiving the write command.

15. The tag of claim 14, further comprising:

means for receiving at the tag a command to erase data stored in the user memory of the tag;

means for clearing the user memory flag in the first memory bank in response to receiving the command to erase; and

means for erasing data stored in the second memory bank in response to receiving the command to erase.

16. A radio frequency identification (RFID) tag, comprising:

an antenna;

a memory that includes a first memory bank and a second memory bank, wherein the second memory bank is configured as a user memory;

a demodulator configured to demodulate a communication signal from a RFID reader, wherein the demodulated communication signal includes a write command to write data into user memory of the tag; and

control logic configured to set a user memory flag in the first memory bank and write the data into a second memory bank of the tag based on receipt of the write command.

17. The tag of claim 16, wherein the tag is a Gen 2 tag, wherein the first memory bank is an Electronic Product Code (EPC) memory bank, wherein the user memory flag is bit 15 hex of the EPC memory bank.

18. The tag of claim 16, wherein the write command specifies a write of the data into the second memory bank and a set of a bit of the first memory bank that represents the user memory flag.

19. The tag of claim 18, wherein the write command further specifies a write of additional data into at least one of a third memory bank or a fourth memory bank of the tag.

20. The tag of claim 18, wherein the write command further specifies a write of additional data into the first memory bank.

21. The tag of claim 16, wherein the write command includes the data for user memory, wherein the control logic includes a logic module configured to set the user memory flag upon receipt of the data for user memory.

22. The tag of claim 21, wherein the logic module is configured to set the user memory flag prior to the data being written into the second memory bank.

23. The tag of claim 21, wherein the logic module is configured to set the user memory flag after the data is written into the second memory bank.

24. The tag of claim 21, wherein the logic module is configured to determine whether the second memory bank stores no data prior to the data being written into the second memory bank, and the logic module is configured to set the user memory flag in the first memory bank if the logic module determined that the second memory bank stores no data prior to the writing step.

25. The tag of claim 16, wherein the demodulator is further configured to demodulate a reader communication signal that includes a command to erase data stored in the user memory of the tag;

and

wherein the control logic is further configured to clear the user memory flag in the first memory bank and erase data stored in the second memory bank based on receipt of the command to erase.

26. The tag of claim 16, wherein the demodulator is further configured to demodulate a reader communication signal that includes a command to erase data stored in the user memory of the tag;

wherein the control logic includes a logic module configured to determine whether the second memory bank will store no data after execution of the command to erase, and to clear the user memory flag in the first memory bank if it is determined that the second memory bank will store no data after execution of the command to erase; and

wherein the control logic is further configured to erase data stored in the second memory bank specified in the command to erase.

27. The tag of claim 16, further comprising:

a cyclic redundancy check (CRC) calculator configured to perform a CRC calculation of bits stored in the first memory bank to account for the setting of the user memory flag.

28. The tag of claim 25, further comprising:

a cyclic redundancy check (CRC) calculator configured to perform a CRC calculation of bits stored in the first memory bank to account for the clearing of the user memory flag.

29. The tag of claim 16, further comprising:

a modulator coupled to the antenna;

wherein the modulator is configured to modulate a response to a reader communication signal.

30. The tag of claim 16, further comprising:

a substrate; and

an integrated circuit (IC) die mounted to the substrate, wherein the memory, demodulator, and control logic are in the IC die;

wherein the antenna is formed on the substrate.