Passive circuits for de-multiplexing display inputs

• US 20080001867A1
• Filed: 06/29/2006
• Published: 01/03/2008
• Est. Priority Date: 06/29/2006
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Chui, Clarence, Lewis, Alan, Mignard, Marc M.
• Granted Patent: US 7,777,715 B2
• Time in Patent Office: Days
• US Class Current: 345/85
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26
• CPC Class Codes: G09G 2310/0218 with collection of electrodes in groups for n-dimensional addressing
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3466 based on interferometric effect

Abstract

A display array which can reduce the row connections between the display and the driver circuit and methods of manufacturing and operating the same are disclosed. In one embodiment, a display device comprises an array of MEMS display elements and a plurality of voltage dividers coupled to the array and configured to provide row output voltages to drive the array, wherein each row is connected to at least two inputs joined by a voltage divider.

Claims

1. A display device comprising:

an array of microelectromechanical system (MEMS) display elements; and

a plurality of passive impedance network circuits coupled to said array and configured to provide row output voltages to drive said array, each passive impedance network comprising at least two inputs and at least one output to a row of display elements, wherein said row output is controlled by said inputs.

2. The device of claim 1, wherein each passive impedance network circuit comprises a resistor network.

3. The device of claim 1, wherein each passive impedance network circuit comprises a voltage divider.

4. The device of claim 3, wherein each voltage divider further comprises:

two or more resistors;

a first terminal to which a control voltage is applied;

a second terminal to which a row driving voltage is applied;

a third terminal coupled to a row of display elements and configured to provide said row output voltage to drive said row.

5. The device of claim 4, wherein all voltage dividers are divided into groups of N voltage dividers and one input of all voltage dividers of each group is connected to the same row driving voltage, wherein N is an integer larger than 1.

6. The device of claim 5, wherein there are totally at least N control voltages and each control voltage is applied to one and only one voltage divider within each of substantially all groups.

7. The device of claim 3, wherein said voltage dividers are fabricated in parallel with the process used to fabricate said array.

8. The device of claim 3, wherein said voltage dividers are formed on the periphery of said array.

9. The device of claim 3, further comprising:

a display;

a processor that is in electrical communication with said display, said processor being configured to process image data;

a memory device in electrical communication with said processor.

10. The device of claim 9, further comprising:

a first controller configured to send at least one voltage to said display; and

a second controller configured to send at least a portion of said image data to said first controller.

11. The device of claim 10, further comprising:

an image source module configured to send said image data to said processor.

12. The device of claim 11, wherein said image source module comprises at least one of a receiver, transceiver, and transmitter.

13. The device of claim 9, further comprising:

an input device configured to receive input data and to communicate said input data to said processor.

14. The device of claim 3, wherein each voltage divider further comprises:

a first terminal to which a control voltage is applied;

a second terminal to which a row driving voltage is applied;

a third terminal coupled to a row of display elements and configured to provide said row output voltage to drive said row; and

two or more resistors connected in series between the first and the second terminal;

wherein the second terminal is connected to each of the first and second terminal through one or more resistors.

15. The device of claim 14, wherein each row driving voltage is applied to one and only one voltage divider.

16. The device of claim 14, wherein the first terminal of all voltage dividers is connected to the same control voltage.

17. The device of claim 14, wherein the control voltage is a voltage of a constant value.

18. A display device comprising:

an array of microelectromechanical system (MEMS) display elements formed as a set of intersecting rows and columns;

a row input lead for each row;

a first voltage input connected through a first series impedance to a first row input lead; and

a second voltage input connected through a second series impedance to said first row input lead.

19. The display device of claim 18, additionally comprising a third voltage input connected through a third series impedance to said first row input lead.

20. The display device of claim 18, wherein said first voltage input is coupled to a first plurality of row input leads through a respective set of series impedances.

21. The display device of claim 20, wherein said second voltage input is coupled to a second plurality of row input leads through a respective set of series impedances.

22. The display of claim 21, wherein said first plurality is different from said second plurality.

23. A display device comprising:

means for displaying image data; and

means for demultiplexing one or more row driving voltages and providing demultiplexed voltages to said displaying means.

24. The device of claim 23, wherein said displaying means comprises one or more MEMS display elements.

25. The device of claim 23, wherein said demultiplexing means comprises one or more voltage dividers.

26. A method of making a display device, the method comprising:

forming an array of microelectromechanical system (MEMS) display elements on a substrate; and

forming a plurality of passive impedance network circuits on the same or a different substrate, each comprising at least two inputs and an output, wherein at least some of said passive impedance network circuits are coupled to said array.

27. The method of claim 26, wherein each passive impedance network circuit comprises a resistor network.

28. The method of claim 26, wherein each passive impedance network circuit comprises a voltage divider.

29. The method of claim 28, wherein the steps of forming said array and forming said plurality of voltage dividers comprise performing at least some common processing steps.

30. The method of claim 28, wherein the steps of forming said array and forming said plurality of voltage dividers can be performed in parallel.

31. The method of claim 28, wherein said array and said voltage dividers are formed on a common substrate.

32. The method of claim 28, wherein said voltage dividers are formed on the periphery of said array.

33. A display device as made by the method of claim 28.

34. A method of demultiplexing a row driving voltage in a row by row addressing scheme of a display device, said method comprising:

applying said row driving voltage of a selected voltage to a plurality of rows through a set of series impedances;

applying a first control voltage to a first one of said plurality of rows through a first series impedance; and

applying a second control voltage to a second one of said plurality of rows through a second series impedance.

35. A display device comprising:

an array of microelectromechanical system (MEMS) display elements;

a row input lead for each row of said array;

a first voltage input connected through a first series impedance to a first row input lead and connected through a second series impedance to a second row input lead.

36. A display device comprising:

an array of microelectromechanical system (MEMS) display elements having N row inputs to said array;

a display driver circuit having n row driver outputs, wherein n is less than N, and

a passive impedance network having said n row driver outputs as inputs, and having N row driver outputs that are coupled to said N row inputs to said array.

37. The display device of claim 36, wherein said passive impedance network comprises a network of resistors.

38. The display device of claim 37, wherein said passive impedance network includes only resistors as impedance components.

39. The display device of claim 36, wherein said passive impedance network is additionally coupled to at least one control input.