Liquid crystal display and method for fabricating the same

• US 20080002074A1
• Filed: 12/22/2006
• Published: 01/03/2008
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Kim, Young-Joo, Lee, Seok-Woo
• Granted Patent: US 7,652,727 B2
• Time in Patent Office: Days
• US Class Current: 349/38
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: G02F 2202/104 poly-Si

Abstract

A liquid crystal display and a method for fabricating the same are disclosed. The method for fabricating a liquid crystal display includes preparing an insulating substrate defining a pixel portion divided into a thin film transistor region and a storage region, sequentially forming a polycrystalline silicon film and a storage electrode film on an entire surface of the substrate, selectively patterning the storage electrode film and the polycrystalline silicon film to form a pixel pattern that covers the pixel portion, and selectively removing the storage electrode film in the thin film transistor region to simultaneously form a first active layer in the thin film transistor region and form a storage electrode in the storage region, wherein the active layer is formed of the polycrystalline silicon film and the storage electrode is formed of the storage electrode film.

Claims

1. A method for fabricating a liquid crystal display, comprising:

preparing an insulating substrate having a first circuit portion, a second circuit portion, and a pixel portion divided into a thin film transistor region and a storage region;

forming a polycrystalline silicon film and a storage electrode film on an entire surface of the substrate;

patterning the storage electrode film and the polycrystalline silicon film to form a pixel pattern that covers the pixel portion; and

removing the storage electrode film in the thin film transistor region to simultaneously form a first active layer in the thin film transistor region and a storage electrode in the storage region,

wherein the first active layer is formed of the polycrystalline silicon film and the storage electrode is formed of the storage electrode film.

2. The method according to claim 1, further comprising forming an first gate insulating film between the polycrystalline silicon film and the storage electrode film.

3. The method according to claim 2, wherein the pixel pattern is formed by selectively patterning the storage electrode film, the first gate insulating film, and the polycrystalline silicon film.

4. The method according to claim 2, wherein the first gate insulating film is formed of a silicon oxide (SiO₂) film.

5. The method according to claim 2, wherein the storage electrode is formed by removing the storage electrode film in the thin film transistor region and maintaining the first gate insulating film from the pixel pattern in the thin film transistor region.

6. The method according to claim 2, wherein the storage electrode film and the first gate insulating film is removed in the thin film transistor region.

7. The method according to claim 1, wherein the storage electrode film is formed of an N+ silicon film.

8. The method according to claim 1, wherein the storage electrode film is formed of a conductive layer.

9. The method according to claim 1, wherein the active layer and the storage electrode are formed using a diffraction mask.

10. The method according to claim 1, wherein the active layer and the storage electrode are formed using a half-tone mask.

11. The method according to claim 1, further comprising:

forming a gate electrode of the pixel portion on the active layer of the thin film transistor region of the pixel portion and a common line on the storage electrode;

forming source and drain regions of the pixel portion in the first active layer below each side of the gate electrode of the pixel portion;

forming a passivation film on the substrate having the source and drain regions of the pixel portion;

patterning the passivation film to form first and second contact holes that expose the source region and the drain region, respectively;

filling the first contact hole of the passivation film to form a source electrode connected with the source region and filling the second contact hole of the passivation film to form a drain electrode connected with the drain region of the pixel portion; and

forming source and drain electrode patterns, the source electrode pattern covering the source electrode and the drain electrode pattern covering the drain electrode.

12. The method according to claim 11, further comprising forming a second gate insulating film on the pixel portion of the substrate.

13. The method according to claim 11, wherein the second contact hole is formed to simultaneously expose the drain region of the pixel portion and a part of the storage electrode.

14. The method according to claim 11, wherein the passivation film is formed by depositing and activation annealing a silicon oxide film on the substrate having the source and drain regions of the pixel portion, and depositing and hydrogenation annealing a silicon nitride film on the substrate having the activated silicon oxide film.

15. The method according to claim 11, wherein the passivation film is formed by sequentially forming a silicon oxide film and a silicon nitride film on the substrate having the source and drain regions of the pixel portion, and simultaneously performing activation of the silicon oxide film and hydrogenation of the silicon nitride film after annealing the silicon nitride film and the silicon oxide film.

16. The method according to claim 11, wherein the passivation film is formed by forming a silicon oxide film and a silicon nitride film on the substrate having the source and drain regions of the pixel portion.

18. The method according to claim 16, further comprising:

forming a first gate electrode of the circuit portion on the third active layer;

forming first source and drain regions of the circuit portion on the third active layer below both sides of the first gate electrode of the circuit portion;

forming a gate electrode of the pixel portion and a second gate electrode of the circuit portion on the first and second active layers, respectively;

forming source and drain regions of the pixel portion in the first active layer below both sides of the gate electrode of the pixel portion and simultaneously forming second source and drain regions of the circuit portion in the second active layer below both sides of the second gate electrode of the circuit portion;

forming a passivation film on the substrate having the second source and drain regions of the circuit portion;

patterning the passivation film to form first/second, third/fourth, and fifth/sixth contact holes to respectively expose the source and drain regions of the pixel portion, the second source and drain regions of the circuit portion, and the first source and drain regions of the circuit portion;

filling the first, third, and fifth contact holes on the passivation film to form a source electrode of the pixel portion connected with the source region of the pixel portion, a second source electrode of the circuit portion connected with the second source region of the circuit portion, and a first source electrode of the circuit portion connected with the first source region of the circuit portion,

simultaneously filling the second, fourth and sixth contact holes on the passivation film to form a drain electrode of the pixel portion connected with the drain region of the pixel portion, a second drain electrode of the circuit portion connected with the second drain region of the circuit portion, and a first drain electrode of the circuit portion connected with the first drain region of the circuit portion; and

forming a source electrode pattern of the pixel portion to cover the source electrode of the pixel portion, and first and second source electrode patterns of the circuit portion, which respectively cover the first and second source electrodes of the circuit portion, and at the same time forming a drain electrode pattern of the pixel portion, which covers the drain electrode of the pixel portion, and first and second drain electrode patterns of the circuit portion, which respectively cover the first and second drain electrodes of the circuit portion.

17. A method for fabricating a liquid crystal display, comprising:

preparing an insulating substrate having a pixel portion and a circuit portion, the pixel portion being divided into a thin film transistor region and a storage region, and the circuit portion being divided into an n-channel thin film transistor region and a p-channel thin film transistor region;

sequentially forming a polycrystalline silicon film and a storage electrode film on an entire surface of the substrate;

selectively patterning the storage electrode film and the polycrystalline silicon film to form a pixel pattern that covers the pixel portion and first and second circuit patterns that respectively cover the n-channel thin film transistor region and the p-channel thin film transistor region of the circuit portion; and

selectively removing the storage electrode film of the thin film transistor region of the pixel portion from the pixel pattern to form a storage electrode in the storage region and a first active layer in the thin film transistor region of the pixel portion, and simultaneously forming second and third active layers that respectively cover the n-channel thin film transistor region and the p-channel thin film transistor region,

wherein the first active layer being formed of a polycrystalline silicon film exposed by the storage electrode.

19. A liquid crystal display, comprising:

an insulating substrate having a pixel portion divided into a thin film transistor region and a storage region;

a first active layer formed on the substrate to cover at least the thin film transistor region; and

a storage electrode formed on the first active layer to selectively cover the storage region.

20. The liquid crystal display according to claim 19, wherein the first active layer includes a polycrystalline silicon film.

21. The liquid crystal display according to claim 19, further comprising an insulating film interposed between the first active layer and the storage electrode.

22. The liquid crystal display according to claim 19, wherein the storage electrode includes an N+ silicon film.

23. The liquid crystal display according to claim 19, wherein the storage electrode includes a metal film.

24. The liquid crystal display according to claim 19, further comprising a buffer layer interposed between the insulating substrate and the first active layer.

25. The liquid crystal display according to claim 19, further comprising:

a gate electrode of the pixel portion and a common line formed on the substrate having the storage electrode;

source and drain regions of the pixel portion in the first active layer below both sides of the gate electrode of the pixel portion;

a passivation film on the substrate having the source region of the pixel portion and the drain region;

first and second contact holes in the passivation film respectively exposing the source region of the pixel portion and the drain region;

a source electrode of the pixel portion filling the first contact hole on the passivation film and connected with the source region of the pixel portion, and a drain electrode of the pixel portion filling the second contact on the passivation film and connected with the drain region of the pixel portion; and

a source electrode pattern of the pixel portion covering the source electrode of the pixel portion, and a drain electrode pattern of the pixel portion covering the drain electrode of the pixel portion.

26. The liquid crystal display according to claim 25, further comprising a second gate insulating film interposed between the insulating substrate having the storage electrode and the gate electrode of the pixel portion and the common line.

27. The liquid crystal display according to claim 26, wherein the second gate insulating film includes a silicon oxide (SiO₂) film.

28. The liquid crystal display according to claim 25, wherein the second contact hole simultaneously exposes a portion of the drain region and a portion of the storage electrode.

29. The liquid crystal display according to claim 25, wherein the passivation film includes at least one of a single silicon nitride film (SiNx), a layer of silicon oxide film (SiO₂)/silicon nitride film (SiNx), and a layer of silicon oxide film (SiO₂)/silicon nitride film (SiNx)/silicon oxide film (SiO₂).

30. A liquid crystal display, comprising:

an insulating substrate having a pixel portion and a circuit portion, the pixel portion being divided into a thin film transistor region and a storage region, and the circuit portion being divided into an n-channel thin film transistor region and a p-channel thin film transistor region;

a first active layer covering the thin film transistor region of the pixel region, a second active layer covering the n-channel thin film transistor region, and a third active layer covering the p-channel thin film transistor region, the first, second, and third active layers being formed on the insulating substrate at the same level; and

a storage electrode on the substrate having the third active layer to cover the storage region.

31. The liquid crystal display according to claim 30, further comprising:

a gate electrode of the pixel portion and first and second gate electrodes of the circuit portion respectively on the first, third and second active layers;

a source region of the pixel portion and a drain region in the first active layer below both sides of the gate electrode of the pixel portion, second source and drain regions of the circuit portion in the second active layer below both sides of the second gate electrode of the circuit portion, and first source and drain regions of the circuit portion in the third active layer below both sides of the first gate electrode of the circuit portion;

a passivation film formed on the substrate having the first source and drain regions of the circuit portion;

first, second, third, fourth, fifth and sixth contact holes respectively exposing the source region of the pixel portion and the drain region, the second source and drain regions of the circuit portion, and the first source and drain regions of the circuit portion;

a source electrode of the pixel portion, a second source electrode of the circuit portion, and a first source electrode of the circuit portion respectively connected with the source region of the pixel portion, the second source region of the circuit portion, and the first source region of the circuit portion filling the first, third and third contact holes on the passivation film,

a drain electrode of the pixel portion, a second source electrode of the circuit portion and a first drain electrode of the circuit portion respectively connected with the drain region of the pixel portion, the second source region of the circuit portion and the first drain region of the circuit portion by filling the second, fourth and sixth contact holes on the passivation film; and

a source electrode pattern of the pixel portion, which covers the source electrode of the pixel portion, and first and second source electrode patterns of the circuit portion, which respectively cover the first and second source electrodes of the circuit portion, and at the same time forming a drain electrode pattern of the pixel portion, which covers the drain electrode of the pixel portion, and first and second drain electrode patterns of the circuit portion, which respectively cover the first and second drain electrodes of the circuit portion.