CAPACITOR ARRAY MANAGEMENT

• US 20080002332A1
• Filed: 06/29/2006
• Published: 01/03/2008
• Est. Priority Date: 06/29/2006
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chen, Hung-I
• Granted Patent: US 7,554,789 B2
• Time in Patent Office: Days
• US Class Current: 361/328
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A capacitor array comprising a plurality of unit capacitors, each having first and second electrode plates. The first electrode plates are commonly connected via first routings. The second electrode plates are grouped and connected to a plurality of nodes via second routings. The second routings connected to one node and another do not overlap in the capacitor array. The second electrode plates connected to the same node conglomerate as a group and no second electrode plate connected to another node is located in the group.

Claims

1. A capacitor array, comprising:

a plurality of unit capacitors, each having first and second electrode plates;

wherein the first electrode plates are connected via first routings, and the second electrode plates are grouped and connected to a plurality of nodes via second routings, wherein second routings connected to one node and another do not overlap in the capacitor array, and each of the second electrode plates connected to the same node conglomerate as a sub-capacitor, and no second electrode plate connected to another node is located in the sub-capacitor.

2. The capacitor array as claimed in claim 1, wherein the nodes respectively receive a binary signal.

3. The capacitor array as claimed in claim 1, wherein the relationship of capacitance associated with the nodes obeys an exponent of two and differs from node to node.

4. The capacitor array as claimed in claim 1, wherein the nodes are arranged on the same side of the capacitor array.

5. The capacitor array as claimed in claim 1, wherein half of the unit capacitors are grouped together and have a sawtooth-shaped edge along a diagonal of the capacitor array, half of the unit capacitors from the other half are grouped together, and so forth.

6. The capacitor array as claimed in claim 1, further comprising a plurality of dummy capacitors uniformly distributed around the periphery.

7. The capacitor array as claimed in claim 1, wherein the first routings are formed with a first metal layer and the second routings a second metal layer.

8. A capacitor comprising identical capacitor arrays as claimed in claim 1, wherein the capacitor arrays are arranged symmetrically in a horizontal or vertical orientation.

9. The capacitor as claimed in claim 8, wherein the second routings of the capacitor arrays are routed out to a plurality of signal rails, respectively associated with one of the nodes, between the capacitor arrays.

10. The capacitor as claimed in claim 9, wherein the signal rails are formed with a conducting layer other than a conducting layer for the second routings of the second electrode plates.

11. A capacitor comprising identical capacitor arrays as claimed in claim 1, wherein the capacitors are arranged symmetrically in horizontal and vertical orientation.

12. The capacitor as claimed in claim 11, wherein the second routings of the capacitor arrays are routed out to a plurality of signal rails, respectively associated with one of the nodes, between the capacitor arrays.

13. The capacitor as claimed in claim 12, wherein the signal rails are formed with a conducting layer other than a conducting layer for the second routings of the second electrode plates.

14. A capacitor array layout technique, comprising:

providing a capacitor array comprising a plurality of unit capacitors, each having first and second electrode plates, wherein the first electrode plates are commonly connected via first routings and the second electrode plates are connected to a plurality of nodes via second routings; and

dividing the second electrode plates into groups each associated with one of the nodes such that the second routings connected to one node and another do not overlap in the capacitor array, and each of the second electrode plates connected to the same node conglomerate as a sub-capacitor, and no second electrode plate connected to another node is located in the sub-capacitor.

15. The capacitor as claimed in claim 14, wherein dividing the second electrode plates into groups further comprises grouping half of the unit capacitors as a first group of the sub-capacitors, grouping half of the unit capacitors from the other half as a second group of the sub-capacitors, and so forth;

wherein the first group of the sub-capacitors has a sawtooth-shaped edge along a diagonal of the capacitor array.