Partial Page Fail Bit Detection in Flash Memory Devices

• US 20080002468A1
• Filed: 06/30/2006
• Published: 01/03/2008
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Hemink, Gerrit Jan
• Granted Patent: US 7,355,892 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A flash memory device, and a method of operating the same, is disclosed. The array of the flash memory device is arranged in pages of memory cells, each page having memory cells associated into groups of memory cells within the page for purposes of fail bit detection in program verification. For example, these groups may correspond to sectors within the page. In a programming operation, the verify process determines whether each group of memory cells within the page has fewer than a selected ignore bit limit for the sector. If not, additional programming is required for the insufficiently programmed cells in the page. By applying a fail bit detection threshold for each of multiple groups within the page, the efficiency of error correction coding in the flash memory is improved. A similar verify and fail bit detection approach may be used in erase and soft programming operations.

Claims

1. A flash memory device, comprising:

a memory array comprised of a plurality of memory cells arranged into pages, each page having a number of memory cells sufficient to store data for a plurality of groups of memory cells;

row decode circuitry for selecting a page of memory cells;

a data register for receiving input data for each memory cell in a selected page;

a plurality of sense amplifiers coupled to the memory array for sensing the contents of memory cells in a selected page;

circuitry for selectively biasing memory cells in the array to program the memory cells in a selected page responsive to input data for the page;

a plurality of group fail bit detector circuits, coupled to the sense amplifiers and each associated with one of the plurality of groups in a page, for counting a number of memory cells in its associated group that has a programmed state not corresponding to the input data associated with that memory cell; and

control logic circuitry for controlling a programming sequence for the selected page responsive to the numbers of memory cells counted by the plurality of group fail bit detector circuits for the page.

2. The memory device of claim 1, wherein each of the plurality of sense amplifiers compares the sensed contents of an associated memory cell in the selected page with the input data associated with that memory cell, and communicates the result to the associated one of the plurality of group fail bit detector circuits.

3. The memory device of claim 2, wherein the plurality of sense amplifiers compare the sensed contents with the input data in a verify operation;

and wherein the row decode applies a verify control gate voltage to the memory cells in the selected page in the verify operation.

4. The memory device of claim 1, further comprising:

a fail detection circuit, coupled to each of the plurality of group fail bit detection circuits and to the control logic circuitry, for comparing the counted number of memory cells from each of the plurality of group fail bit detection circuits and for communicating a signal corresponding to the comparing to the control logic circuitry.

5. The memory device of claim 1, wherein a first plurality of memory cells associated with each of the groups of each of the pages corresponds to a data portion, and wherein a second plurality of memory cells associated with each of the groups of each of the pages corresponds to a parity bit portion.

6. The memory device of claim 1, wherein the control logic circuitry controls the programming sequence by iteratively applying programming pulses to control gates of the memory cells in the selected page, verifying the programmed state, and repeating the applying and verifying responsive to the numbers of memory cells counted by the plurality of group fail bit detector circuits for the page.

7. The memory device of claim 6, further comprising:

a programming analog-to-digital converter for generating a programming voltage to be applied by the row decode circuitry in programming pulses.

8. The memory device of claim 7, wherein the control logic circuitry controls the programming analog-to-digital converter to increase the programming voltage for successive iterations of the programming sequence.

9. The memory device of claim 1, wherein each of the groups of memory cells in a page corresponds to a sector of data.

10. The memory device of claim 1, wherein each of the groups of memory cells in a page corresponds to a plurality of sectors of data.

11. The memory device of claim 1, wherein each of the memory cells is capable of storing more than two data states.

12. The memory device of claim 1, wherein the memory cells are arranged in NAND fashion in the array.

13. A flash memory system, comprising:

a flash memory controller, comprising;

a host interface, for coupling to a host system;

a device interface; and

control circuitry for generating memory addresses; and

a flash memory device comprising;

a memory array comprised of a plurality of memory cells arranged into pages, each page having a number of memory cells sufficient to store data for a plurality of groups of memory cells;

row decode circuitry for selecting a page of memory cells;

a data register for receiving input data for each memory cell in a selected page;

a plurality of sense amplifiers coupled to the memory array for sensing the contents of memory cells in a selected page;

circuitry for selectively biasing memory cells in the array to program the memory cells in a selected page responsive to input data for the page;

a plurality of group fail bit detector circuits, coupled to the sense amplifiers and each associated with one of the plurality of groups in a page, for counting a number of memory cells in its associated group that has a programmed state not corresponding to the input data associated with that memory cell; and

control logic circuitry, coupled to the flash memory controller, for forwarding an address signal to the row decode circuitry to select a page corresponding to a memory address provided by the flash memory controller, and for controlling a programming sequence for the selected page responsive to the numbers of memory cells counted by the plurality of group fail bit detector circuits for the page.

14. The memory system of claim 13, wherein each of the plurality of sense amplifiers compares the sensed contents of an associated memory cell in the selected page with the input data associated with that memory cell, and communicates the result to the associated one of the plurality of group fail bit detector circuits.

15. The memory system of claim 14, wherein the plurality of sense amplifiers compare the sensed contents with the input data in a verify operation;

and wherein the row decode applies a verify control gate voltage to the memory cells in the selected page in the verify operation.

16. The memory system of claim 13, wherein the flash memory device further comprises:

a fail detection circuit, coupled to each of the plurality of group fail bit detection circuits and to the control logic circuitry, for comparing the counted number of memory cells from each of the plurality of group fail bit detection circuits and for communicating a signal corresponding to the comparing to the control logic circuitry.

17. The memory system of claim 13, wherein a first plurality of memory cells associated with each of the groups of each of the pages corresponds to a data portion, and wherein a second plurality of memory cells associated with each of the groups of each of the pages corresponds to a parity bit portion.

18. The memory system of claim 13, wherein the control logic circuitry controls the programming sequence by iteratively applying programming pulses to control gates of the memory cells in the selected page, verifying the programmed state, and repeating the applying and verifying responsive to the numbers of memory cells counted by the plurality of group fail bit detector circuits for the page.

19. The memory system of claim 18, further comprising:

a programming analog-to-digital converter for generating a programming voltage to be applied by the row decode circuitry in programming pulses.

20. The memory system of claim 19, wherein the control logic circuitry controls the programming analog-to-digital converter to increase the programming voltage for successive iterations of the programming sequence.

21. The memory system of claim 13, wherein each of the groups of memory cells in a page corresponds to a sector of data.

22. The memory system of claim 13, wherein each of the groups of memory cells in a page corresponds to a plurality of sectors of data.

23. The memory system of claim 13, wherein each of the memory cells is capable of storing more than two data states.

24. The memory system of claim 13, wherein the memory cells are arranged in NAND fashion in the array.