Surface emitting semiconductor device

• US 20080002750A1
• Filed: 06/26/2007
• Published: 01/03/2008
• Est. Priority Date: 06/29/2006
• Status: Abandoned Application

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: Doi, Hideyuki, Onishi, Yutaka
• Application Number:
  US11/819,246
• Publication Number:
  US 20080002750A1
• Time in Patent Office: Days
• US Class Current: 372/50.11
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01S 2304/04 MOCVD or MOVPE
• CPC Class Codes: H01S 5/18308 having a special structure for lateral current or light confinement
• CPC Class Codes: H01S 5/305 characterised by the doping materials used in the laser structure
• CPC Class Codes: H01S 5/3054 p-doping
• CPC Class Codes: H01S 5/3095 Tunnel junction

Abstract

A surface emitting semiconductor device comprises an active layer, a p-type III-V compound semiconductor layer, an n-type III-V compound semiconductor layer, and a burying layer. The active layer includes a primary surface, the primary surface having first and second areas. The p-type III-V compound semiconductor layer is provided on the first and second areas of the primary surface of the active layer. The n-type III-V compound semiconductor layer is provided on the second area of the primary surface of the active layer. The n-type III-V compound semiconductor is provided on the p-type III-V compound semiconductor layer. The n-type III-V compound semiconductor and the p-type III-V compound semiconductor layer form a tunnel junction. The n-type III-V compound semiconductor layer contains tellurium as an n-type dopant. The burying layer is made of III-V compound semiconductor. The n-type III-V compound semiconductor layer is covered with the burying layer.

Claims

1. A surface emitting semiconductor device comprising:

an active layer including a primary surface, the primary surface having first and second areas;

a p-type III-V compound semiconductor layer provided on the first and second areas of the primary surface of the active layer;

an n-type III-V compound semiconductor layer provided on the second area of the primary surface of the active layer, the n-type III-V compound semiconductor layer being provided on the p-type III-V compound semiconductor layer, the n-type III-V compound semiconductor layer and the p-type III-V compound semiconductor layer forming a tunnel junction, and the n-type III-V compound semiconductor layer containing tellurium as an n-type dopant; and

a burying layer made of III-V compound semiconductor, the n-type III-V compound semiconductor layer being buried by the burying layer.

2. The surface emitting semiconductor device according to claim 1, wherein the p-type III-V compound semiconductor layer contains carbon as a p-type dopant.

3. The surface emitting semiconductor device according to claim 1, wherein a thickness of the n-type III-V compound semiconductor layer is equal to or less than 50 nanometers.

4. The surface emitting semiconductor device according to claim 1, wherein the n-type III-V compound semiconductor layer includes In_XGa_1-XAs (0.05≦

X≦

0.4).

5. The surface emitting semiconductor device according to claim 1, wherein the n-type III-V compound semiconductor layer and p-type III-V compound semiconductor layer form a type II superlattice structure.

6. The surface emitting semiconductor device according to claim 5, wherein the n-type III-V compound semiconductor layer has a top and a side, and the burying layer covers the top and the side of the n-type III-V compound semiconductor layer.

7. The surface emitting semiconductor device according to claim 1, wherein the n-type III-V compound semiconductor layer and p-type III-V compound semiconductor layer form a type I superlattice structure.

8. The surface emitting semiconductor device according to claim 7, wherein the n-type III-V compound semiconductor layer has a top and a side, and the burying layer covers the top and the side of the n-type III-V compound semiconductor layer.

9. The surface emitting semiconductor device according to claim 1, wherein the p-type III-V compound semiconductor layer is made of InGaAs, and the n-type III-V compound semiconductor layer is made of one of the following:

InGaAs;

GaAsSb;

GaInNAs; and

GaInNAsSb.

10. The surface emitting semiconductor device according to claim 1, further comprising:

an n-type semiconductor substrate;

a first distributed Bragg reflector; and

a second distributed Bragg reflector,

wherein the p-type III-V compound semiconductor layer, the active layer and the n-type III-V compound semiconductor layer are provided between the first distributed Bragg reflector and the second distributed Bragg reflector, and the first and second distributed Bragg reflectors are mounted on the n-type semiconductor substrate.

11. The surface emitting semiconductor device according to claim 1, further comprising a contact layer provided on the burying layer and the contact layer is doped with an n-type dopant.

12. The surface emitting semiconductor device according to claim 11, wherein the burying layer is doped with an n-type dopant.

13. The surface emitting semiconductor device according to claim 12, wherein the n-type dopant in the burying layer is different form the n-type dopant in the contact layer.

14. The surface emitting semiconductor device according to claim 12, wherein the n-type dopant in the burying layer is Si and the n-type dopant in the contact layer is Te.

15. The surface emitting semiconductor device according to claim 1, further comprising:

a first distributed Bragg reflector; and

a second distributed Bragg reflector,

wherein the p-type III-V compound semiconductor layer, the active layer and the n-type III-V compound semiconductor layer are provided between the first distributed Bragg reflector and the second distributed Bragg reflector.

16. The surface emitting semiconductor device according to claim 1, further comprising:

a contact layer provided on the burying layer;

a first distributed Bragg reflector; and

a second distributed Bragg reflector provided on the contact layer,

wherein the p-type III-V compound semiconductor layer, the active layer, the n-type III-V compound semiconductor layer and the contact layer are provided between the first distributed Bragg reflector and the second distributed Bragg reflector.

17. The surface emitting semiconductor device according to claim 16, wherein the n-type III-V compound semiconductor layer has a mesa, and the first distributed Bragg reflector, the n-type III-V compound semiconductor layer, the active layer and the second distributed Bragg reflector are arranged on a predetermined axis.

18. The surface emitting semiconductor device according to claim 16, wherein the second distributed Bragg reflector includes first III-V compound semiconductor layers and second III-V compound semiconductor layers, and the first III-V compound semiconductor layers and second III-V compound semiconductor layers are arranged alternately.

19. The surface emitting semiconductor device according to claim 16, wherein the second distributed Bragg reflector includes first dielectric layers and second dielectric layers, and the dielectric layers and second dielectric layers are arranged alternately.

20. The surface emitting semiconductor device according to claim 1, wherein the surface emitting semiconductor device includes a surface emitting semiconductor laser.