Wafer-level assembly of heat spreaders for dual IHS packages

• US 20080003719A1
• Filed: 06/30/2006
• Published: 01/03/2008
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lu, Daoqiang, Hu, Chuan, Baskaran, Rajashree
• Granted Patent: US 7,476,568 B2
• Time in Patent Office: Days
• US Class Current: 438/113
• CPC Class Codes: H01L 21/4882 Assembly of heatsink parts
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68309 Auxiliary support including alignment aids
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 24/27 Manufacturing methods
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An embodiment of the present invention is a technique to fabricate a package. A heat spreader (HS) array on a HS support substrate is formed. The HS array has a plurality of heat spreaders. A diced wafer supported by a wafer support substrate (WSS) is formed. The diced wafer has a plurality of thin dice. The thin dice in the diced wafer are bonded to the heat spreaders in the HS array to form HS-bonded thin dice between the HS support substrate and the WSS.

Claims

1. A method comprising:

forming a heat spreader (HS) array on a HS support substrate, the HS array having a plurality of heat spreaders;

forming a diced wafer supported by a wafer support substrate (WSS), the diced wafer having a plurality of thin dice; and

bonding the thin dice in the diced wafer to the heat spreaders in the HS array to form HS-bonded thin dice between the HS support substrate and the WSS.

2. The method of claim 1 further comprising:

releasing the HS support substrate from the HS array;

mounting the bonded diced wafer onto a dicing tape;

releasing the WSS from the diced wafer; and

assembling an HS-bonded thin die into a package.

3. The method of claim 1 wherein forming the HS array comprises:

fabricating a carrier template having a plurality of cavities;

placing the plurality of heat spreaders in the cavities;

placing the HS support substrate coated with a layer of silicone on the plurality of heat spreaders, the heat spreaders adhering to the layer of silicone; and

picking up the plurality of heat spreaders from the carrier template.

4. The method of claim 1 wherein forming the diced wafer comprises:

mounting a wafer on a wafer support substrate (WSS);

thinning the wafer to a desired thickness;

depositing a backside metallization (BSM) and solder layer on backside of the thinned wafer; and

dicing the thinned wafer into the plurality of thin dice.

5. The method of claim 1 wherein bonding the thin dice comprises:

aligning the diced wafer to the HS array to match the thin dice with the heat spreaders; and

reflowing the solder layer of the BSM under pressure on at least one of the WSS and the HS support substrate.

6. The method of claim 2 wherein releasing the HS support substrate comprises:

removing the HS support substrate by vacuum pressure.

7. The method of claim 2 wherein releasing the WSS comprises:

decomposing adhesive between the WSS and the wafer by laser.

8. The method of claim 2 wherein assembling the HS-bonded thin die comprises:

picking the HS-bonded thin die from the dicing tape;

placing the HS-bonded thin die on a substrate;

dispensing an underfill between the HS-bonded thin die and the substrate;

applying a thermal interface material (TIM) on the HS; and

attaching an integral heat spreader to the TIM and the substrate.

9. A package comprising:

a substrate;

a die assembly attached to the substrate, the die assembly comprising;

a thin die having a thickness,

a first thermal interface material (TIM) deposited on the thin die, and

a first heat spreader (HS) attached to the thin die through the first TIM;

a second TIM attached to the first HS; and

a second heat spreader attached to the substrate and the second TIM, the second heat spreader enclosing the die assembly.

10. The package of claim 9 further comprising:

an underfill dispensed between the die assembly and the substrate.

11. The package of claim 9 wherein the thickness is less than 50 μ

m.

12. The package of claim 9 wherein the first TIM has a remelting point higher than 250°

C.

13. The package of claim 9 wherein the first TIM has thickness less than the second TIM.

14. The package of claim 9 wherein the first TIM has thickness of approximately 5 μ

m.

15. The package of claim 9 wherein the first heat spreader is approximately equal to the thin die in size.

16. A system comprising:

a front end processing unit to receive and transmit a radio frequency (RF) signal, the RF signal being converted to digital data;

a digital processor coupled to the front end processing unit to process the digital data; and

a memory device coupled to the digital processor, the memory device being packaged in a package, the package comprising;

a substrate,

a die assembly attached to the substrate, the die assembly comprising;

a thin die having a thickness,

a first thermal interface material (TIM) deposited on the thin die, and

a first heat spreader (HS) attached to the first TIM,

a second TIM attached to the first HS, and

a second heat spreader attached to the substrate and the second TIM, the

second heat spreader enclosing the die assembly.

17. The system of claim 16 further comprising:

an underfill dispensed between the die assembly and the substrate.

18. The system of claim 16 wherein the thickness is less than 50 μ

m.

19. The system of claim 16 wherein the first TIM has a remelting point higher than 250°

C.

20. The system of claim 16 wherein the first TIM has thickness less than the second TIM.

21. The system of claim 16 wherein the first TIM has thickness of approximately 5 μ

m.

22. The system of claim 16 wherein the first heat spreader is approximately equal to the thin die in size.