Communications circuit and method with reduced power consumption

• US 20080004008A1
• Filed: 06/30/2006
• Published: 01/03/2008
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Alexander Thomas, Charles Nicholas, Ridler, Oliver, Nicol, Christopher John
• Granted Patent: US 8,831,603 B2
• Time in Patent Office: Days
• US Class Current: 455/434
• CPC Class Codes: H04W 52/02 Power saving arrangements in wired systems H04L12/12; signaling of mobile application services, e.g. low battery notifications H04W4/20
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: H04W 52/146 Uplink power control
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A method of operating a communications circuit with at least one control channel and at least one data channel includes the steps of monitoring the at least one control channel, powering a receiver portion of the circuit when the at least one control channel indicates that data is to be received, and refraining from powering the receiver portion when the at least one control channel indicates that data is not to be received. The circuit can operate, for example, under the 3GPP HSDPA standard. Where desired, the clock and power supply to the receiver portion and a bit rate processing portion can be independently gated.

Claims

1. A method of operating a communications circuit with at least one control channel and at least one data channel, comprising the steps of:

monitoring said at least one control channel;

powering a receiver portion of said circuit when said at least one control channel indicates data is to be received; and

refraining from powering said receiver portion when said at least one control channel indicates that data is not to be received.

2. The method of claim 1, wherein said circuit is configured for operation under a 3GPP HSDPA standard, said at least one control channel comprises an HS-SCCH control channel, and said at least one data channel comprises an HS-PDSCH channel.

3. The method of claim 1, further comprising the additional step of:

refraining from powering a bit rate processing block of said circuit when no bit rate processing is required and no retransmission is pending.

4. The method of claim 3, further comprising performing the additional steps of:

powering said bit rate processing block of said circuit; and

clock-gating said bit rate processing block of said circuit;

when;

no bit rate processing is required; and

a retransmission is pending.

5. The method of claim 3, further comprising the additional step of maintaining power to a buffer interposed between said receiver portion and said bit rate processing block substantially continuously during said operating of said circuit.

6. The method of claim 3, further comprising the additional steps of:

maintaining power to a buffer interposed between said receiver portion and said bit rate processing block when at least one of said receiver portion and said bit rate processing block is powered; and

refraining from powering said buffer interposed between said receiver portion and said bit rate processing block when neither said receiver portion nor said bit rate processing block is powered.

7. A communications circuit for operation with at least one control channel and at least one data channel, comprising:

a control channel receiver module configured to monitor said at least one control channel; and

a data channel receiver module coupled to said control channel receiver module, said data channel receiver module being configured to be powered-on when said at least one control channel indicates data is to be received and being configured to be powered-down when said at least one control channel indicates that data is not to be received.

8. The circuit of claim 7, wherein said circuit is configured for operation under a 3GPP HSDPA standard, said at least one control channel comprises an HS-SCCH control channel, and said at least one data channel comprises an HS-PDSCH channel.

9. The circuit of claim 7, further comprising a bit rate processing block coupled to said data channel receiver module, wherein said bit rate processing block is configured to be powered down when:

no bit rate processing is required; and

no retransmission is pending.

10. The circuit of claim 9, further comprising a tracking portion, wherein said tracking portion is coupled to said bit rate processing block and is configured to determine that no retransmission is pending.

11. The circuit of claim 9, wherein said bit rate processing block is configured to be powered and clock-gated when:

no bit rate processing is required; and

a retransmission is pending.

12. The circuit of claim 11, further comprising a tracking portion, wherein said tracking portion is coupled to said bit rate processing block and is configured to determine that said retransmission is pending.

13. The circuit of claim 9, further comprising a buffer interposed between said data channel receiver module and said bit rate processing block, wherein power to said buffer is maintained substantially continuously during operation of said circuit.

14. The circuit of claim 9, further comprising a buffer interposed between said data channel receiver module and said bit rate processing block, wherein power to said buffer is maintained when at least one of said data channel receiver module and said bit rate processing block is powered and power to said buffer is cut when neither said data channel receiver module nor said bit rate processing block is powered.

15. The circuit of claim 14, further comprising a data channel clock and supply control module coupled to said control channel receiver module, said data channel receiver module, said bit rate processing block, and said buffer, said data channel clock and supply control module being configured to receive control signals from said control channel receiver module and to control:

power to said data channel receiver module;

power to said bit rate processing block;

power to said buffer; and

clock-gating of said bit rate processing block.

16. The circuit of claim 15, wherein said data channel receiver module comprises a data receiver clock, and wherein said data channel clock and supply control module is further configured to control clock-gating of said data receiver clock.

17. The circuit of claim 16, wherein said data channel clock and supply control module comprises a tracking portion, wherein said tracking portion is coupled to said bit rate processing block and is configured to determine whether said retransmission is pending.

18. The circuit of claim 7, wherein said circuit is formed as an integrated circuit.

19. A communications apparatus for operation with at least one control channel and at least one data channel, comprising:

a radio frequency (RF) front end configured to receive signals carrying said at least one control channel and said at least one data channel and to output in-phase and quadrature (IQ) samples therefrom;

a control channel receiver module coupled to said RF front end and configured to receive said IQ samples therefrom for monitoring said at least one control channel;

a data channel receiver module coupled to said control channel receiver module and coupled to said RF front end so as to receive said IQ samples therefrom, said data channel receiver module being configured to be powered-on when said at least one control channel indicates data is to be received and being configured to be powered-down when said at least one control channel indicates that data is not to be received.

20. The apparatus of claim 19, wherein said apparatus is configured for operation under a 3GPP HSDPA standard, said at least one control channel comprises an HS-SCCH control channel, and said at least one data channel comprises an HS-PDSCH channel.