Passive mirroring through concurrent transfer of data to multiple target devices

• US 20080005385A1
• Filed: 06/30/2006
• Published: 01/03/2008
• Est. Priority Date: 06/30/2006
• Status: Abandoned Application

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Lubbers, Clark E., DeCenzo, David P.
• Application Number:
  US11/479,365
• Publication Number:
  US 20080005385A1
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 11/2087 with a common controller

Abstract

Method and apparatus for passively mirroring data to multiple storage locations. Data are concurrently transferred by a source device to at least first and second target devices over a common pathway. Respective first and second acknowledgement signals are supplied to the source device in response to the data transfer. In some embodiments, the data are synchronously clocked into first-in-first-out (FIFO) elements of the first and second target devices using a common clock signal. In other embodiments, the data are transferred to the first device at a first rate and are transferred to the second device at a second rate different from the first rate. The source device preferably comprises a functional controller core (FCC) of a multi-device array, and the target devices preferably comprise separate buffer managers. The source device further preferably updates a metadata structure in response to receipt of the first and second acknowledgement signals.

Claims

1. An apparatus comprising a source device configured to concurrently transfer data to first and second target devices over a common pathway and to receive respective first and second acknowledgement signals from the respective first and second target devices in response thereto.

2. The apparatus of claim 1, wherein the data are synchronously clocked into first-in-first-out (FIFO) elements of the first and second target devices using a common clock signal.

3. The apparatus of claim 1, wherein the data are transferred to the first device at a first rate and are transferred to the second device at a second rate different from the first rate.

4. The apparatus of claim 1, wherein the source device comprises a functional controller core (FCC) of a multi-device array.

5. The apparatus of claim 4, wherein the first and second target devices each respectively comprise a buffer manager of the multi-device array.

6. The apparatus of claim 1, wherein the source device and the first target device are disposed in a first integrated circuit package, and wherein the second target device is disposed in a second integrated circuit package in communication with the first integrated circuit package.

7. The apparatus of claim 1, wherein the source device further operates to update a metadata structure in response to receipt of the first and second acknowledgement signals.

8. The apparatus of claim 1, wherein data are characterized as parity data generated and transferred on-the-fly by the source device to the respective first and second target devices.

9. A method comprising concurrently transferring data from a source device to first and second target devices via a common pathway, and transmitting first and second acknowledgement signals to the source device to respectively confirm receipt of the data by the respective first and second target devices.

10. The method of claim 9, wherein the transferring step comprises synchronously clocking the data packet into the first and second target devices using a common clock signal.

11. The method of claim 9, wherein the transferring step comprises transferring the data to the first device at a first rate and transferring the data to the second device at a second rate.

12. The method of claim 9, wherein the first acknowledgement signal is transmitted from the first target device to the source device via a first pathway, and wherein the second acknowledgement signal is transmitted from the second target device to the source device via a second pathway.

13. The method of claim 9, wherein the source device of the transferring step comprises a functional controller core of a multi-device array.

14. The method of claim 13, wherein the first and second target devices of the transferring step each respectively comprise a buffer manager of the multi-device array.

15. The method of claim 9, wherein the transferring step comprises at least one direct memory access (DMA) operation by the source device.

16. The method of claim 9, wherein the source device and the first target device are disposed in a first integrated circuit package, and wherein the second target device is disposed in a second integrated circuit package in communication with the first integrated circuit package.

17. The method of claim 16, wherein the first integrated circuit package forms a first intelligent storage processor (ISP), and wherein the second integrated circuit package forms a second ISP in communication with the first ISP via an E-Bus.

18. The method of claim 9, further comprising a step of updating a metadata structure in response to receipt of the first and second acknowledgement signals.

19. The method of claim 9, wherein the data transferred by the source device comprises parity data generated by said source device.