Optimized performance and power access to a shared resource in a multiclock frequency system on a chip application

• US 20080005437A1
• Filed: 11/02/2006
• Published: 01/03/2008
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gupta, Vikram, Lambert, Ed
• Granted Patent: US 7,555,585 B2
• Time in Patent Office: Days
• US Class Current: 710/241
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A request from a first processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the first processor at a first clock frequency. A request from a second processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the second processor at a second clock frequency that is lower than the first clock frequency.

Claims

1. A method comprising:

receiving a request from a first processor for access to a shared resource in a computing system;

providing access by the first processor to the shared resource at a first clock frequency;

receiving a request from a second processor for access to the shared resource; and

providing access by the second processor to the shared resource at a second clock frequency, wherein the second clock frequency is lower than the first clock frequency.

2. The method of claim 1, wherein the shared resource comprises a shared memory device.

3. The method of claim 1, wherein the first processor comprises a central processing unit.

4. The method of claim 1, wherein the second processor comprises a processor selected from the group consisting of an encoder and a decoder.

5. The method of claim 1, wherein the second processor comprises a direct memory access device.

6. The method of claim 1, further comprising:

generating a first clock signal having a frequency equal to the first clock frequency;

generating a second clock signal having a frequency equal to the second clock frequency;

providing the first clock signal to the shared resource to clock access to the shared resource when the first processor accesses the shared resource; and

providing the second clock signal to the shared resource to clock access to the shared resource when the second processor accesses the shared resource.

7. The method of claim 5, wherein generating the second clock signal comprises removing pulses from the first clock signal.

8. The method of claim 1, wherein the computing system comprises:

a battery; and

a system on a chip, wherein the system on a chip is powered by the battery.

9. The method of claim 1, wherein the first clock frequency is at least twice the second clock frequency.

10. A system comprising:

a first processor configured to access a shared resource in a computing system;

a second processor configured to access a shared resource;

clock circuitry configured to provide a clock signal for clocking access to the shared resource, wherein the clock circuitry is configured to provide the clock signal with a first clock frequency when the first processor accesses the shared resource and wherein the clock circuitry is configured to provide the clock signal with a second clock frequency when the second processor accesses the shared resource.

11. The system of claim 10, wherein the shared resource comprises a memory device.

12. The system of claim 10, wherein the first processor comprises a central processing unit.

13. The system of claim 10, wherein the second processor comprises a processor selected from the group consisting of an encoder and a decoder.

14. The system of claim 10, wherein the second processor comprises a direct memory access device.

15. The system of claim 10, further comprising a battery configured to power the system and

wherein the system comprises a system on a chip,

wherein the system of a chip comprises the first processor, the second processor, and the clock circuitry.

16. The system of claim 10, wherein the first clock frequency is at least twice the second clock frequency.

17. The system of claim 10, further comprising a memory controller configured to:

(i) receive requests from the first and second processors for access to the shared resource and grant requests and (ii) grant a processor access to the shared resource in response to a request.

18. The system of claim 10, further comprising a pulse swallower configured to generate the clock signal with the second frequency by receiving an input signal having a frequency equal to the first frequency and selectively removing pulses from the input signal.

19. The system of claim 10, further comprising circuitry for receiving an encoded audio signal, decoding the audio signal, and outputting the decoded signal to an audio output device.

20. The system of claim 19, further comprising a speaker for playing the decoded signal.