Fast transition from low-speed mode to high-speed mode in high-speed interfaces

• US 20080005455A1
• Filed: 05/17/2007
• Published: 01/03/2008
• Est. Priority Date: 05/17/2006
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lee, Ming-Ju, Chen, Lin, Morein, Steven, Macri, Joseph
• Granted Patent: US 7,752,476 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.

Claims

1. A method comprising:

transmitting data from a first device to a second device at a first data rate;

transmitting a speed transition command to the second device to enable transmission of data to the second device at a second data rate that is higher than the first data rate;

transmitting data from the first device to the second device at the second data rate after an idle period required to allow transition of circuitry in the second device to the second data rate; and

transmitting data from the first device to the second device at the first data rate during a transition period comprising a period of time in which the circuitry of the second device is adapting to operation at the second data rate.

2. The method of claim 1 wherein the first device comprises a memory controller and the second device comprises a random access memory device.

3. The method of claim 2 further comprising:

generating a reference clock signal that is configured to operate as both a high-speed mode clock and a low-speed mode clock; and

synchronizing a timing circuit in the memory device to a lock to the reference clock signal.

4. The method of claim 3 further comprising:

generating the low-speed mode clock by switching the timing circuitry to a first state; and

generating the high-speed mode clock by switching the timing circuit to a second state.

5. The method of claim 4 wherein the first state of the timing circuit comprises the reference clock signal routed through a low speed timing logic circuit within the memory device, and wherein the second state of the timing circuit comprises the reference clock signal routed through a frequency multiplier circuit within the memory device.

6. The method of claim 5 wherein the frequency multiplier circuit comprises a phase locked loop circuit within the memory device.

7. The method of claim 1 wherein the idle period comprises a defined number of clock cycles of the reference clock signal.

8. The method of claim 7 wherein the defined number of clock cycles is contained in the speed transition command.

9. The method of claim 6 wherein the speed transition command only activates the circuitry of the second device to operate at the second data rate, the method further comprising transmitting the low-to-high speed transition command after one or more commands are sent during the transition period.

10. The method of claim 8 wherein the circuitry of the second device is queried to determine transition to the second data rate, and wherein the idle period is ended by a positive response to the query.

11. A method for communicating data in an electronic system, comprising:

transmitting data via an interface at a first data rate using first timing circuitry;

transmitting data via the interface at a second data rate using second timing circuitry; and

transitioning from transmitting data at the first data rate to transmitting data at the second data rate, by

initializing the second timing circuitry; and

continuing to transmit data at the first data rate during a period required to initialize the second timing circuitry.

12. The method of claim 11 wherein the second data rate is higher than the first data rate.

13. The method of claim 12 wherein the first timing circuitry comprises a reference clock signal gated through a low-speed logic circuit and a switch, and wherein the second timing circuit comprises the reference clock signal gated through a clock multiplier circuit and the switch.

14. The method of claim 13 wherein the switch comprises a multiplexer controlled by a select signal generated by a first device controlling transmission of data over the interface.

15. The method of claim 14 wherein the first device comprises a memory controller coupled to a random access memory device over the interface.

16. The method of claim 15 wherein the clock multiplier circuit comprises a phase locked loop coupled to the multiplexer.

17. A memory control circuit comprising:

a transceiver sending and receiving data to and from a memory over an interface at a first data rate;

a command circuit transmitting a speed transition command to initialize a timing circuit within the memory to perform data operations at a second data rate that is higher than the first data rate, the command circuit further transmitting a select signal to signal the timing circuit to switch between operation at the first data rate and operation at the second data rate, wherein the memory performs data operations at said first data rate during the transition period.

18. The memory control circuit of claim 17 wherein the timing circuit within the memory comprises a first timing portion routing a reference clock signal through a low-speed logic circuit and a switch, and a second portion routing the reference clock signal gated through a clock multiplier circuit and the switch.

19. The memory control circuit of claim 18 wherein the clock multiplier circuit comprises a phase locked loop coupled to the multiplexer.

20. The memory control circuit of claim 19 wherein the switch comprises a multiplexer controlled by the select signal generated by the memory control circuit.

21. A method comprising:

communicating data to and from a controller device over an interface at a first data rate;

communicating data to and from the controller device at a second data rate that is higher than the first data rate in response to a speed transition command;

adapting, during a transition period, one or more circuits to communicate data at the second data rate;

communicating data to and from the controller device at the first data rate during the transition period; and

communicating data to and from the controller device at the second data rate after the transition period.

22. The method of claim 22 wherein the speed transition command is received from the controller device over the interface in a memory device storing at least a portion of the data.

23. An apparatus comprising:

a transceiver circuit communicating data to and from a controller device over an interface at a first data rate, and at a second data rate that is higher than the first data rate; and

a logic circuit training the transceiver, during a transition period, to communicate data over the interface at the second data rate from the first data rate in response to a speed transition command, wherein the transceiver circuit communicates data to and from the controller device at the first data rate during the transition period, and communicates data to and from the controller device at the second data rate after the transition period.

24. The apparatus of claim 23 the speed transition command is received from a controller device over an interface, the apparatus further comprising a memory core storing at least a portion of the communicated data.

25. A system comprising:

a memory device having a memory core storing data and a timing circuit synchronizing memory operations consisting of transmission and reception of data to the memory core; and

a controller device coupled to the memory device over an interface, the controller device having a transceiver sending and receiving data to and from the memory device over the interface at a first data rate, and a command circuit transmitting a speed transition command over the interface to initialize the timing circuit within the memory device to perform memory operations at a second data rate that is higher than the first data rate, the command circuit further transmitting a select signal to signal the timing circuit to switch between memory operations at the first data rate and operation at the second data rate, wherein the memory device performs memory operations at said first data rate during the transition period.

26. The system of claim 25 wherein the system comprises a computing device.

27. The system of claim 26 wherein the computing device is selected from the group consisting of:

a personal computer, a workstation, a handheld computing device, a digital television, a media playback device, and a game console.