Cache coherency controller management
First Claim
1. A method, comprising:
- receiving a message in a cache controller;
directing the message into a processing pipeline in the cache controller;
analyzing the message in the processing pipeline in an output issue logic module;
directing the message to an output queue when an output port is unavailable or when the message cannot bypass the output queue; and
sending the message to the output port when the output port is available or when the output queue can be bypassed.
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Accused Products
Abstract
Methods and apparatus to manage cache coherency are disclosed. In one embodiment, an apparatus comprises a first processor comprising a first processing unit, a first cache memory, and a first coherence controller, and an input/output module having one or more output ports. The first coherence controller comprises an arbitration logic module to direct a message into a processing pipeline and an output issue logic module. The output issue logic module analyzes a message in the processing pipeline, directs the message to an output queue when an output port is unavailable or when the message cannot bypass the output queue, and sends the message to the output port when one or more output ports are available or when the output queue can be bypassed.
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Citations
22 Claims
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1. A method, comprising:
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receiving a message in a cache controller; directing the message into a processing pipeline in the cache controller; analyzing the message in the processing pipeline in an output issue logic module; directing the message to an output queue when an output port is unavailable or when the message cannot bypass the output queue; and sending the message to the output port when the output port is available or when the output queue can be bypassed. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An apparatus comprising:
a first processor comprising a first processing unit, a first cache memory, and a first coherence controller, and an input/output module having one or more output ports, the first coherence controller comprising; an arbitration logic module to direct a message into a processing pipeline; and an output issue logic module to; analyze a message in the processing pipeline; direct the message to an output queue when an output port is unavailable or when the message cannot bypass the output queue; and send the message to the output port when one or more output ports are available or when the output queue can be bypassed. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A system, comprising:
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a memory module; a first processor comprising a first processing unit, a first cache memory, and a first coherence controller, and an input/output module having one or more output ports, the first coherence controller comprising; an arbitration logic module to direct a message into a processing pipeline; and an output issue logic module to; analyze a message from the processing pipeline in an output logic module; direct the message to an output queue when an output port is unavailable or when the message cannot bypass the output queue; and send the message to the output port when one or more output ports are available or when the output queue can be bypassed. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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Specification