Dual-Port SRAM Memory Using Single-Port Memory Cell
First Claim
1. A semiconductor memory system comprising:
- a memory array comprising a plurality of single-port memory cells;
two access ports, including a first port and a second port; and
an access arbiter configured to arbitrate synchronous or asynchronous access requests on the first and second ports by synchronizing and prioritizing these access requests.
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Accused Products
Abstract
A dual-port memory system is implemented using single-port memory cells. An access arbiter having a synchronization circuit is used to prioritize and synchronize the access requests associated with the two ports. The access arbiter can also prioritize and synchronize refresh requests, in the case where the single-port memory cells require refresh. Access requests on the two ports and the refresh requests can be asynchronous. The access arbiter synchronizes the various requests by latching the requests into first-stage registers when a row access signal (RAS) is activated, and subsequently latching the contents of the first-stage registers into second-stage registers after a selected delay.
15 Citations
21 Claims
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1. A semiconductor memory system comprising:
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a memory array comprising a plurality of single-port memory cells; two access ports, including a first port and a second port; and an access arbiter configured to arbitrate synchronous or asynchronous access requests on the first and second ports by synchronizing and prioritizing these access requests. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of operating a memory system comprising:
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storing data in single-port memory cells of a memory array; accessing the memory array in response to access requests on a first port; accessing the memory array in response to access requests on a second port; and arbitrating asynchronous access requests on the first and second ports by synchronizing and prioritizing these access requests. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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Specification