Updating a memory block without status logging

• US 20080005503A1
• Filed: 05/26/2006
• Published: 01/03/2008
• Est. Priority Date: 05/26/2006
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Rudelic, John
• Granted Patent: US 7,603,587 B2
• Time in Patent Office: Days
• US Class Current: 711/156
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: H04W 8/245 from a network towards a terminal

Abstract

A technique to update a memory block without status logging is presented. An update file includes a pre-update and a post-update information verification code (IVC) for each block to be updated. By comparing the IVCs to an IVC of a block of memory, an update status may be determined.

Claims

1. A method comprising:

utilizing a pair of received information verification codes (IVCs) from an update file to determine a status of an update to memory.

2. The method as recited in claim 1, wherein utilizing the received IVC comprises:

calculating a current IVC of a block of memory; and

comparing the current IVC with the pair of received IVCs.

3. The method as recited in claim 2, wherein the pair of received IVCs includes a pre-update IVC and a post-update IVC for the block of memory.

4. The method as recited in claim 2, wherein if the current IVC is not equal to either of the pair of received IVCs, the block of memory has been partially updated.

5. The method as recited in claim 2, further comprising updating the block of memory using difference information from the update file.

6. The method as recited in claim 1, further comprising:

receiving the update file wirelessly.

7. A method comprising:

transmitting an update file to a portable device, the update file including multiple information verification codes (IVCs) and difference information;

wherein the portable device is configured to use the difference information to update units of memory and use the multiple IVCs to verify status of the update to the units of memory.

8. The method as recited in claim 7, wherein the multiple IVCs are hash codes.

9. The method as recited in claim 7, wherein the multiple IVCs are error correction codes (ECCs).

10. The method as recited in claim 7, wherein the transmitting includes transmitting over the air (OTA).

11. The method as recited in claim 7, wherein the units of memory are blocks of flash memory.

12. The method as recited in claim 7, wherein the multiple IVCs include a pre-update IVC and a post-update IVC for each unit of memory to be updated.

13. An apparatus comprising:

a memory having a first portion to store a received update file, the update file including multiple information verification codes (IVCs) and difference information; and

a state machine configured to use the multiple IVCs to determine a status of an update to a second portion of the memory.

14. The apparatus as recited in claim 13, wherein the multiple IVCs include a pre-update IVC and a post-update IVC for each block of memory in the second portion of memory to be updated.

15. The apparatus as recited in claim 13, wherein to update the portion of memory, the state machine is further configured to:

calculate a current IVC of a block of memory; and

compare the current IVC with a first IVC of the multiple IVCs.

16. The apparatus as recited in claim 15, wherein if the current IVC and the first IVC are not equal and the current IVC and a second IVC from the multiple IVCs are not equal, the block has been partially updated.

17. The apparatus as recited in claim 15, wherein the difference information is used to update the information stored in the second portion of the memory.

18. A system comprising:

an antenna to receive an update file;

a memory having a first portion to store the update file, the update file including multiple information verification codes (IVCs) and difference information; and

a state machine configured to use the multiple IVCs to determine a status of an update to a second portion of the memory.

19. The system as recited in claim 18, wherein the multiple IVCs include a pre-update IVC and a post-update IVC for each block of memory in the second portion of memory to be updated.

20. The system as recited in claim 18, wherein to update the portion of memory, the state machine is further configured to:

calculate a current IVC of a block of memory; and

compare the current IVC with a first IVC of the multiple IVCs.

21. The system as recited in claim 18, wherein the difference information is used to update the information stored in the second portion of the memory.

22. An apparatus comprising:

a machine accessible medium; and

instructions stored on the machine accessible medium, wherein the instructions, when executed by a processing system, cause the processing system to;

utilize a pair of received information verification codes (IVCs) from an update file to determine a status of an update to memory.

23. The apparatus as recited in claim 22, wherein to utilize the pair of received IVCs the processing system is caused to:

calculate a current IVC of a block of memory; and

compare the current IVC with the pair of received IVCs.

24. The apparatus as recited in claim 23, wherein the pair of received IVCs includes a pre-update IVC and a post-update IVC for the block of memory.