Synchronous memory read data capture

• US 20080005518A1
• Filed: 06/30/2006
• Published: 01/03/2008
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: McKenzie, Robert, Gillingham, Peter
• Granted Patent: US 7,685,393 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/1066 Output synchronization

Abstract

A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up. Another embodiment of the invention is a simple, low latency clock domain crossing circuit based on the DQS latched sample of the counter.

Claims

1. A method for controlling a synchronous memory comprising:

establishing a read data path delay between the memory and a memory controller by;

the memory controller writing an initialization sequence to predetermined locations of the memory;

the memory controller sending a read command to the memory to read the predetermined locations and receiving returned data signals;

a predetermined time after sending the read command, the memory controller sampling the returned data signals to produce an initialization sample;

using the initialization sample to determine the read delay between the memory and the memory controller.

2. The method of claim 1 further comprising:

on an ongoing basis executing reads from the memory by;

sending a read command;

in response to the read command receiving a data signal and receiving a data strobe signal synchronously with the data signal;

enabling the data strobe signal as a function of the read delay.

3. The method of claim 1 wherein sampling the returned data comprises:

sampling each bit of Gray code with four clock phases.

4. The method of claim 3 wherein:

the Gray code is an N-bit Gray code having 2^N codewords;

the memory controller writing a Gray code initialization sequence to predetermined locations of the memory comprises writing each of the 2^N codewords to a pair of addresses within 2^N+1 consecutive addresses.

5. The method of claim 4 wherein:

writing the 2^N codewords to 2^N+1 consecutive addresses comprises writing N bits to each of the 2^N+1 addresses;

sampling each bit of the Gray code with four clock phases comprises sampling a respective read signal in respect of which an nth bit of the N-bit Gray code was written with the four clock phases, where n=0, . . . ,N-1.

6. The method of claim 4 wherein:

writing the 2^N codewords to 2^N+1 consecutive addresses comprises writing bits of a respective Gray code codeword g₁, g₂, . . . ,g_N as 4N bits to each of the 2^N+1 addresses by writing g₁,g₁,g₁,g₁, . . . g_N,g_N,g_N,g_N to pairs of addresses;

sampling each bit of the Gray code with four clock phases comprises;

in response to the read command, receiving 4N data signals as said returned data signals;

sampling N data signals with a first clock phase;

sampling another N data signals with a second clock phase;

sampling another N data signals with a third clock phase; and

sampling another N data signals with a fourth clock phase.

7. The method of claim 6 wherein N=2.

8. The method of claim 6 wherein N=3.

9. The method of claim 1 further comprising:

for each of a plurality of read delays, storing an expected initialization sample;

wherein;

using the initialization sequence to determine the read delay between the memory and the memory controller comprises looking up the read delay stored for the initialization sequence.

10. The method of claim 9 wherein for each of a plurality of read delays, storing an expected initialization sequence comprises determining a state of a counter for each read delay, and storing the counter state in association with the initialization sequence, the method further comprising:

on an ongoing basis, for each read command, starting the counter after sending a read command, and enabling the data strobe when the code counter reaches the counter state for the determined read delay.

11. The method of claim 10 wherein:

the counter is a hardware implemented Gray code counter that increments on quarter clock phases.

12. The method of claim 10 wherein the counter is an RTL counter that increments on quarter clock phases.

13. The method of claim 1 further comprising:

on an ongoing basis determining if there is clock drift, and if so, updating the read delay.

14. The method of claim 1 further comprising:

disabling the data strobe signal accounting for read burst length and consecutive read commands.

15. The method of claim 1 further comprising for each delay:

storing an enable count indicating when to enable the data strobe;

storing a disable count indicating when to disable the data strobe; and

storing an indication of whether to sample at a 0 degree or 180 degree clock phase for data recovery.

16. The method of claim 1 further comprising re-timing read data signals to an RTL clock.

17. A memory controller adapted to implement a method for controlling a memory that has a bidirectional read/write bus with source synchronous clocking and a bidirectional data strobe, the method comprising:

measuring a read delay between the memory and the memory controller by;

the memory controller writing a Gray code initialization sequence to predetermined locations of the memory;

the memory controller sending a read command to the memory to read the predetermined locations and receiving returned data signals;

a predetermined time after sending the read command, the memory controller sampling the returned data signals to produce an initialization sample;

using the initialization sample to determine the read delay between the memory and the memory controller.

18. A memory controller for controlling a memory that has a bidirectional read/write bus with source synchronous clocking and a bidirectional data strobe, the controller comprising:

a read delay determination circuit and a data strobe enable circuit;

during initialization, the read delay determination circuit determining a read delay between sending a read command to the memory and receiving data signals in return, the read delay determination circuit comprising a circuit for sampling the data at a predetermined time to produce an initialization sample, and a table lookup function that stores a respective read delay in respect of each permutation of the initialization sample;

the data strobe enable circuit being adapted to gate a received DQS as a function of the read delay.

19. The memory controller of claim 18 further comprising at least one of:

a circuit for selecting between a 0°

sample and a 180°

sample; and

a circuit for re-timing the data signals to a main clock.

20. The memory controller of claim 18 wherein the table look-up function stores for each permutation of the initialization sequence:

a data strobe enable count;

a data strobe disable count;

whether to sample at 0 degrees or 180 degrees for normal read operations a memory.

21. A data strobe enable circuit for use with a memory that has a bidirectional read/write bus with source synchronous clocking and a bi-directional data strobe, the data strobe enable circuit comprising:

an input for receiving a data strobe signal having rising and falling edges;

an output for producing a gated data strobe signal;

a multiplexer that gates the data strobe signal as a function of a select input;

a select input generator circuit connected to receive a data strobe enable and data strobe disable;

that sets the select input to select the data strobe signal upon activation of the data strobe enable, and that sets the select input to deselect the data strobe signal upon activation of the data strobe disable and following a next edge of the data strobe signal.

22. The data strobe enable circuit of claim 21 wherein the select input generator circuit comprises:

a first D flip-flop that receives the data strobe enable;

a second D flip-flop that receives the data strobe disable;

an AND gate that combines outputs of the first D flip-flop and the second D flip-flop;

an SR flip-flop that is clocked by the gated data strobe signal, the SR flip-flop having a D input for receiving the output of the second D flip-flop, and having an S input for receiving an output of the AND gate, and having a Q output that functions as the select input such that when the enable input becomes active, the select input asynchronously selects the data strobe signal, and when the data strobe disable input becomes active, the select input reflects this on the next rising edge of the data strobe signal.

23. The data strobe enable circuit of claim 21 further adapted to produce a gated inverse data strobe signal using the select input.

24. The data strobe enable circuit of claim 23 further comprising:

a circuit for selecting between a first mode of operation in which a data strobe signal is received and an inverted data strobe signal generated, and a second mode of operation in which a data strobe signal and an inverted data strobe signal are received.

25. A drift detector circuit comprising:

a first circuit for latching a first value of a first clock phase of a master clock synchronously with an input clock signal;

a second circuit for latching a second value of a second clock phase of the master clock synchronously with the input clock signal;

wherein a change in either the first value or the second value indicates that the input clock signal has drifted relative to the master clock source by at least a predetermined amount.

26. The drift detector circuit of claim 25 wherein:

the first circuit comprises a first D flip-flop, the first D flip-flop connected to receive the input clock signal to a first clock input of the first D flip-flop, having a first D input that receives the first clock phase of the master clock, and having a first Q output that produces the first value; and

the second circuit comprises a second D flip-flop, the second D flip-flop connected to receive the input clock signal to a second clock input of the second D flip-flop, having a second D input that receives the second clock phase of the master clock, and has a second Q output that produces the second value.

27. The drift detector circuit of claim 25 wherein the first clock phase is a 0°

clock based on the master clock, and the second clock phase is a 90°

clock based on the master clock, and the predetermined amount is a quarter clock cycle.

28. The drift detector circuit of claim 26 comprising a master slave DLL to produce the first clock phase and the second clock phase from the master clock.