Methods, Systems, and Computer Program Products for Using a Structured Data Storage System to Provide Access to Addressable Entities in Virtual Address Space

• US 20080005528A1
• Filed: 06/30/2006
• Published: 01/03/2008
• Est. Priority Date: 06/30/2006
• Status: Abandoned Application

• Current Assignee: Scenera Technologies LLC (Scenera Research LLC)
• Original Assignee: Scenera Technologies LLC (Scenera Research LLC)
• Inventors: Morris, Robert P.
• Application Number:
  US11/428,324
• Publication Number:
  US 20080005528A1
• Time in Patent Office: Days
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence

Abstract

Methods, systems, and computer program products for using a structured data storage system (SDSS) to provide access to addressable entities in a virtual address space are disclosed. A memory management system (MMS) is provided including an SDSS to manage a virtual address space. An addressable entity associated with an identifier from the virtual address space is stored in a first memory location using the SDSS within the MMS. The identifier corresponding to the addressable entity is used to locate the first memory location to access the addressable entity from the first memory location during processing of a first machine code instruction including the identifier by a processor.

Claims

1. A method for using a structured data storage system (SDSS) to provide access to addressable entities in a virtual address space, the method comprising:

providing a memory management system (MMS) including an SDSS to manage a virtual address space;

storing an addressable entity associated with an identifier from the virtual address space in a first memory location using the SDSS within the memory management system; and

using the identifier corresponding to the addressable entity to locate the first memory location to access the addressable entity from the first memory location during processing of a first machine code instruction including the identifier by a processor.

2. The method of claim 1 wherein providing a memory management system includes providing at least one of an SDSS page table, an SDSS map table, and an SDSS translation lookaside buffer (TLB).

3. The method of claim 1 wherein the first memory location includes at least one of a random access memory (RAM) location and a memory location in a persistent memory media.

4. The method of claim 1 comprising storing the addressable entity to a second memory location and associating the identifier corresponding to the addressable entity with the second memory location in association with storing the corresponding addressable entity in the second memory location.

5. The method of claim 1 wherein the addressable entity includes one of an executable program function, a program object having an executable component, a virtual register, a parameter, a data variable, and a data constant.

6. The method of claim 1 wherein the first memory location includes a RAM location and wherein the method further comprises, in response to completion of processing of the first machine code instruction, and using the identifier corresponding to the addressable entity to query the memory management system for a second memory location associated with the identifier associated with relocating the addressable entity to access the addressable entity within the RAM location during a subsequent processing of a second machine-code instruction including the identifier by the processor.

7. The method of claim 1 wherein the first memory location includes a RAM location and wherein the method further comprises, in response to completion of processing of the first machine code instruction, storing the addressable entity in a persistent memory location and mapping the addressable entity into a second RAM location and using the identifier corresponding to the addressable entity to query the memory management system for the second RAM location to access the addressable entity within the second RAM location during a subsequent processing of the first machine code instruction.

8. The method of claim 1 wherein the first memory location includes a RAM location and wherein the method further comprises, in response to completion of processing of the first machine code instruction, storing the addressable entity in a persistent memory location and mapping the addressable entity into a second memory location and using the identifier corresponding to the addressable entity to query the SDSS for the second memory location to access the addressable entity within the second memory location during a subsequent processing of the first machine code instruction.

9. The method of claim 1 wherein the identifier corresponding to the addressable entity is associated with a symbol usable within a programming syntax to allow the association of the identifier corresponding to the addressable entity with the first memory location to be resolved at an instruction level within a processor by querying the SDSS for the first memory location.

10. The method of claim 1 wherein the MMS includes a TLB and wherein using the identifier corresponding to the addressable entity to access the addressable entity during processing of the first machine code instruction includes querying the TLB using the identifier to identify a physical address of the first memory location.

11. The method of claim 1 wherein the SDSS includes at least one of an SDSS map table, a TLB, and a page table and wherein using the identifier corresponding to the addressable entity to access the addressable entity during processing of the first machine code instruction includes querying the at least one of an SDSS map table, a TLB, and a page table using the identifier, and comprising calculating a physical address of the first memory location in response to identification of the association of the identifier corresponding to the addressable entity with the first memory location in the at least one of an SDSS map table, a TLB, and a page table.

12. The method of claim 1 wherein the addressable entity includes a code block and wherein the identifier is used to query the SDSS for the first memory location and wherein the first memory location is used to jump to the code block during processing of the first machine code instruction.

13. The method of claim 1 wherein the addressable entity includes a data variable and wherein the method further comprises storing a value in the first memory location using the identifier to query the SDSS for the first memory location during processing of the first machine code instruction.

14. The method of claim 1 wherein the addressable entity includes a data variable and wherein the method further comprises retrieving a value stored in the first memory location using the identifier to query the SDSS for the first memory processing of the first machine code instruction.

15. The method of claim 1 comprising at least one of storing the addressable entity to a storage location associated with the identifier in a persistent memory and retrieving the addressable entity from the storage location in the persistent memory using the identifier.

16. The method of claim 1 wherein the virtual address space is a non-sequential virtual address space.

17. The method of claim 1 wherein the virtual address space includes a non-sequential virtual address space that co-exists with a sequential virtual address space.

18. The method of claim 1 wherein the addressable entity includes one of an executable addressable entity and a non-executable addressable entity.

19. The method of claim 1 wherein using the identifier corresponding to the addressable entity to access the addressable entity from the first memory location includes analyzing the identifier when the identifier is from a non-sequential portion of the virtual address space to determine whether the identifier is an SDSS address

20. The method of claim 19 wherein the MMS includes at least one of an SDSS map table, a TLB, and a page table and wherein, in response to determining that the identifier is an SDSS address, searching for the first memory location within the at least one of an SDSS map table, a TLB, and a page table.

21. The method of claim 19 wherein the MMS includes an SDSS TLB and wherein, in response to determining that the identifier is an SDSS address, searching for the first memory location within the SDSS TLB.

22. The method of claim 19 wherein the SDSS includes a map table and wherein, in response to determining that the identifier is not an SDSS address, searching for the first memory location in the map table.

23. The method of claim 19 wherein the MMS includes a translation lookaside buffer (TLB) and wherein, in response to determining that the identifier is not an SDSS address, searching for the first memory location the TLB.

24. The method of claim 1 wherein the SDSS includes an SDSS map table and wherein using the identifier corresponding to the addressable entity to locate the first memory location includes querying the SDSS for the first memory location to access the addressable entity from the first memory location during processing of the first machine code instruction by indexing the SDSS map table with the identifier to locate the addressable entity within persistent memory.

25. The method of claim 1 wherein the MMS includes at least one of an SDSS map table, a TLB, and a page table and wherein using the identifier corresponding to the addressable entity to locate the first memory location to access the addressable entity from the first memory location includes processing the identifier by indexing the at least one of an SDSS map table, a TLB, and a page table with the identifier to locate the addressable entity within memory.

26. A system for using a structured data storage system (SDSS) to provide access to addressable entities in a virtual address space, the system comprising:

an SDSS configured for managing a virtual address space by assigning an identifier to an addressable entity and associating the identifier corresponding to the addressable entity with a first memory location for storing the corresponding addressable entity; and

a processor configured for using the identifier corresponding to the addressable entity to access the addressable entity from the first memory location within the virtual address space during processing of a machine code instruction.

27. A system for using a structured data storage system (SDSS) to provide access to addressable entities in a virtual address space, the system comprising:

a memory management system (MMS) including a structured data storage system (SDSS) for managing a virtual address space; and

a processor including;

an instruction set processor (ISP) for processing a first machine code instruction that includes an identifier as an operand, where the identifier is from the virtual address space and references an index of a location managed by the SDSS for storing, at the index referenced by the identifier, an association between an addressable entity and a first memory location for storing the addressable entity; and

a memory management unit (MMU) enabled to locate the first memory location associated with the addressable entity stored at the location indexed by the identifier within the MMS to allow the processor to access the addressable entity in the first memory location during the processing of the machine code instruction by the ISP.

28. The system of claim 27 wherein the MMS includes at least one of an SDSS page table, an SDSS map table and an SDSS translation lookaside buffer (TLB).

29. The system of claim 27 wherein the processor is adapted to process a second machine code instruction for storing the addressable entity to a second memory location and wherein the MMS is adapted to associate the identifier corresponding to the addressable entity with the second memory location for storing the corresponding addressable entity.

30. The system of claim 27 wherein the addressable entity is selected from a group consisting of an executable program function, a program object having an executable component, a virtual register, a parameter, a data variable, and a data constant.

31. The system of claim 27 wherein the first memory location includes a first RAM location and wherein the processor is adapted to, in response to completion of processing of the first machine code instruction, store the addressable entity in a persistent memory location, to copy the addressable entity into a second RAM location, to associate the identifier with the second RAM location, and to use the identifier corresponding to the addressable entity to query the MMS for the second RAM location to access the addressable entity within the second RAM location during a subsequent processing of a second machine code instruction by the processor.

32. The system of claim 27 wherein the first memory location includes at least one of a random access memory (RAM) location and a memory location in a persistent memory.

33. The system of claim 27 wherein the identifier corresponding to the addressable entity is associated with a symbol usable within a programming syntax and wherein the MMS is adapted to use the symbol to resolve the association of the identifier corresponding to the addressable entity with the first memory location and wherein the processor is adapted to access the addressable entity at an instruction level by querying the MMS for the first memory location.

34. The system of claim 27 wherein the MMS includes at least one of an SDSS TLB, an SDSS page table, and an SDSS map table and wherein the processor is adapted to use the identifier corresponding to the addressable entity to query the at least one of the SDSS TLB, the SDSS page table, and the SDSS map table to identify a physical address of the first memory location to access the addressable entity during processing of the first machine code instruction.

35. The system of claim 27 wherein the MMS includes at least one of an SDSS map table, a TLB, and a page table and wherein the processor is adapted to use the identifier corresponding to the addressable entity to query the at least one of an SDSS map table, a TLB, and a page table and wherein the processor is further adapted to calculate a physical address of the first memory location in response to identification of the association of the identifier corresponding to the addressable entity with the first memory location in the at least one of an SDSS map table, a TLB, and a page table.

36. The system of claim 27 wherein the addressable entity includes a code block and wherein the processor is adapted to use the identifier to query the SDSS for the first memory location and to jump to the code block during processing of the first machine code instruction.

37. The system of claim 27 wherein the addressable entity includes a data variable and wherein the processor is adapted to use the identifier to query the SDSS for the first memory location and to perform at least one of storing a value in and retrieving a value from the first memory location during processing of the first machine code instruction.

38. The system of claim 27 wherein the processor is adapted to operate within the virtual address space and wherein the processor is further adapted to perform an operation selected from a group consisting of storing the addressable entities associated with an portion of the virtual address space to a persistent memory and retrieving a portion of the addressable entities associated with the active portion of the virtual address space from the persistent memory.

39. The system of claim 27 wherein the virtual address space is a non-sequential address space.

40. The system of claim 27 wherein the virtual address space includes a non-sequential address space and a sequential address space and wherein the processor is adapted to process identifiers from both the non-sequential virtual address space and the sequential virtual address space.

41. The system of claim 40 wherein the processor is adapted to execute an executable system resource associated with an identifier within an address space selected from the sequential virtual address space and the non-sequential virtual address space.

42. The system of claim 27 wherein the addressable entity includes an addressable entity selected from the group consisting of an executable addressable entity and a non-executable addressable entity.

43. The system of claim 27 wherein the processor is adapted to use the identifier corresponding to the addressable entity to access the addressable entity from the first memory location during processing of the first machine code instruction by analyzing the identifier from a non-sequential portion of the virtual address space to determine whether the identifier is a (SDSS) address.

44. The system of claim 43 wherein the MMS includes an SDSS map table and wherein the processor is adapted to, in response to determining that the identifier is an SDSS address, search for the first memory location within the SDSS map table.

45. The system of claim 43 wherein the MMS includes at least one of an SDSS map table, a TLB, and a page table and wherein the processor is adapted to, in response to determining that the identifier is an SDSS address, search for the first memory location within the at least one of an SDSS map table, a TLB, and a page table.

46. The system of claim 43 wherein the SDSS includes a map table and wherein the processor is adapted to, in response to determining that the identifier is not an SDSS address, search for the first memory location in the map table.

47. The system of claim 43 wherein the MMS includes a translation lookaside buffer (TLB) and wherein the processor is adapted to, in response to determining that the identifier is not an SDSS address, search for the first memory location in the TLB.

48. The system of claim 27 wherein the processor is adapted to use the identifier corresponding to the addressable entity to query the SDSS for the first memory location to access the addressable entity from the first memory location during processing of the first machine code instruction.

49. The system of claim 27 wherein the SDSS includes at least one of an SDSS map table, a TLB, and a page table and wherein the processor is adapted to use the identifier corresponding to the addressable entity to query the at least one of an SDSS map table, a TLB, and a page table for the first memory location to access the addressable entity from the first memory location during processing of the first machine code instruction.

50. The system of claim 27 wherein the MMS includes an SDSS translation lookaside buffer (TLB) and wherein the processor is adapted to use the identifier corresponding to the addressable entity to query the SDSS TLB for the first memory location to access the addressable entity from the first memory location during processing of the first machine code instruction.

51. A system for using a structured data storage system to provide access to addressable entities in virtual address space, the system comprising:

means for providing an SDSS to manage a virtual address space;

means for assigning, using the SDSS, an identifier to an addressable entity;

means for associating, within the SDSS, the identifier corresponding to the addressable entity with a first memory location for storing the corresponding addressable entity; and

means for using the identifier corresponding to the addressable entity to access the addressable entity from the first memory location within the virtual address space during processing of a machine code instruction.

52. A computer program product comprising computer-executable instructions embodied in a computer-readable medium for performing steps comprising:

providing an SDSS to manage a virtual address space;

assigning, using the SDSS, an identifier to an addressable entity;

associating, within the SDSS, the identifier corresponding to the addressable entity with a first memory location for storing the corresponding addressable entity; and

using the identifier corresponding to the addressable entity to access the addressable entity from the first memory location during processing of a machine code instruction.