Managing wasted active power in processors

• US 20080005593A1
• Filed: 06/29/2006
• Published: 01/03/2008
• Est. Priority Date: 06/29/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wyatt, David Anthony
• Granted Patent: US 7,882,381 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

Methods of managing wasted active power of processors in computer systems and other electronic devices are disclosed. In one aspect, a method may include counting a number of times that a processor has performed an instruction loop. Then, a determination may be made whether the number of times that the processor has performed the loop is greater than one or more thresholds or other given values. Next, a limit may be imposed on the power of the processor if the number of times that the processor has performed the loop is greater than at least one of the thresholds or given values. Logic to perform such methods is also disclosed, as are systems suitable for incorporating such logic.

Claims

1. A method comprising:

counting a number of times a processor has performed a loop;

determining whether the number of times the processor has performed the loop is greater than one or more values; and

imposing a limit on a power of the processor if the number of times the processor has performed the loop is greater than at least one of the one or more values.

2. The method of claim 1, further comprising:

generating a signature for the loop; and

using the signature to determine that the loop has been performed during said counting.

3. The method of claim 2, wherein said generating the signature comprises using a function.

4. The method of claim 3, wherein the function has properties that:

if outputs generated using the function are different, then corresponding inputs to the function are different; and

equality of the outputs generated using the function suggests equality of corresponding inputs to the function.

5. The method of claim 4, wherein the function comprises a function selected from a hash function and a checksum function.

6. The method of claim 3, wherein said generating the signature for the loop comprises inputting data from instructions of the loop to the function.

7. The method of claim 6, wherein the data comprises opcodes, immediate data, and addresses, natively included with the instructions.

8. The method of claim 2, wherein said generating the signature comprises counting a number of instructions in the loop.

9. The method of claim 8, wherein said counting the number of instructions in the loop comprises counting the number of instructions between hint instructions.

10. The method of claim 1, further comprising:

determining whether a number of instructions executed since a last loop indication instruction is greater than a value; and

if the number of instructions is greater than the value, removing the limit imposed on the power of the processor.

11. The method of claim 1, wherein said imposing the limit on the power of the processor comprises one or more selected from imposing a limit on a frequency of at least a portion of the processor, imposing a limit on a voltage of at least a portion of the processor, and disabling a portion of the processor.

29. The method of claim 1:

further comprising determining if a size of the loop is less than one or more size values; and

wherein said imposing the limit on the power of the processor is conditioned on the size of the loop being less than one or more of the size values.

12. An apparatus comprising:

a counter to count a number of times a processor has performed a loop; and

logic to impose a limit on power of the processor if the number of times the processor has performed the loop is greater than one or more values.

13. The apparatus of claim 12, further comprising:

signature computation logic to compute a signature for the loop; and

signature comparison logic to compare the signature computed for the loop with signatures computed for previously encountered loops to identify the loop during said counting.

14. The apparatus of claim 13, wherein the signature computation logic comprises a function having properties that:

if outputs generated using the function are different, then corresponding inputs to the function are different; and

equality of the outputs generated using the function suggests equality of corresponding inputs to the function.

15. The apparatus of claim 14, wherein the function comprises a function selected from a hash function and a checksum function.

16. The apparatus of claim 12, further comprising:

a second counter to keep a count of the number of instructions in the loop; and

loop identification logic to identify the loop from previously encountered loops using the count of the number of instructions in the loop.

17. The apparatus of claim 12, further comprising instruction examination logic to determine that an instruction is a hint instruction.

18. The apparatus of claim 12, further comprising hardware coupled with the logic to perform one or more selected from imposing a limit on a frequency of at least a portion of the processor, imposing a limit on a voltage of at least a portion of the processor, and disabling a portion of the processor.

19. The apparatus of claim 18, wherein the hardware comprises one or more selected from a fuse, a control, and a circuit, and wherein the portion of the processor comprises a core.

20. A system comprising the apparatus of claim 12, wherein the system further comprises a direct current (DC) power supply to power the apparatus.

30. The apparatus of claim 12, further comprising:

a second counter to keep a count of the number of instructions in the loop; and

logic to condition the imposing of the limit on the power of the processor on the count of the number of instructions in the loop being less than one or more loop size values.

21. A system comprising:

a dynamic random access memory (DRAM);

a main processor coupled with the DRAM;

a power management logic of the main processor, the power management logic including;

a counter to count a number of times the main processor has performed a loop; and

logic to impose a limit on power of the main processor upon determining that the number of times the main processor has performed the loop is greater than one or more thresholds.

22. The system of claim 21, wherein the power management logic further comprises:

signature computation logic to compute a signature for the loop; and

signature comparison logic to compare the signature computed for the loop with signatures computed for previously encountered loops to identify the loop during said counting.

23. The system of claim 22, wherein the signature computation logic comprises a function having properties that:

if outputs generated using the function are different, then corresponding inputs to the function are different; and

equality of inputs to the function are likely equal if corresponding outputs generated using the function are equal.

24. The system of claim 21, wherein the power management logic further comprises:

a second counter to keep a count of the number of instructions in the loop; and

loop identification logic to identify the loop from previously encountered loops using the count of the number of instructions in the loop.

25. The system of claim 21, further comprising one or more selected from a battery and a fuel cell to provide power to the system.

26. An article of manufacture comprising:

a machine-accessible medium that provides instructions that if executed result in a machine performing operations including,

counting a number of times a processor has performed a loop, determining whether the number of times the processor has performed the loop is greater than one or more values, and

imposing a limit on a power of the processor if the number of times the processor has performed the loop is greater than at least one of the one or more values.

27. The article of manufacture of claim 26, wherein the machine-accessible medium further provides instructions that if executed result in the machine performing operations including,

generating a signature for the loop, and

using the signature to determine that the loop has been performed during said counting.

28. The article of manufacture of claim 26, wherein the machine-accessible medium further provides instructions that if executed result in the machine performing operations including,

determining whether a number of instructions executed since a last loop indication instruction is greater than a value, and

if the number of instructions is greater than the value, removing the limit imposed on the power of the processor.