Concurrent thread execution using user-level asynchronous signaling

• US 20080005737A1
• Filed: 06/30/2006
• Published: 01/03/2008
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jacobson, Quinn A., Saha, Bratin, Adl-Tabatabai, Ali-Reza
• Granted Patent: US 8,468,526 B2
• Time in Patent Office: Days
• US Class Current: 718/100
• CPC Class Codes: G06F 2209/521 Atomic
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

Various usage models are provided to utilize a Monitor and Call (“mcall”) instruction that incorporates user-level asynchronous signaling. The various usage models utilize the mcall instruction in a multithreading system in order to enhance concurrent thread execution. Other embodiments are also described and claimed.

Claims

1. A system, comprising:

a first thread unit and a second thread unit;

a memory coupled to the first and second thread units;

a hardware mechanism of the first thread unit to perform an asynchronous control transfer to user code responsive to a write, by the second thread unit, to a selected location of said memory;

said memory further to store software instructions to detect a conflict between two concurrent threads and to utilize said hardware mechanism to trigger said handler code responsive to said conflict.

2. The system of claim 1, wherein:

said memory is a DRAM.

3. The system of claim 1, wherein:

said software instructions include instructions for an atomic multiple-compare, single-swap (“

kcss”

) operation.

4. The system of claim 3, wherein:

said software instructions are further to detect a write operation, by the second thread unit, to a data location that is one of k locations to be monitored by the kcss operation.

5. The system of claim 1, wherein:

said software instructions include instructions for a software transactional memory transaction abort operation.

6. The system of claim 5, wherein:

said software instructions are further to detect a write operation, by the second thread unit, to an input data address for an atomic software transaction being executed by the first thread unit.

7. The system of claim 1, wherein:

said software instructions include instructions for a priority inversion correction operation.

8. The system of claim 7, wherein:

said software instructions are further to detect a write operation, by the second thread unit, to an inversion indicator monitored by the first thread unit.

9. The system of claim 8, wherein:

said software instructions are further to stall execution of the first thread unit and release a software lock held by the first thread unit.

10. A method, comprising:

enabling monitoring of a memory location;

beginning to perform a set of one or more instructions on a first thread unit;

responsive to a write operation to the memory location by a second thread unit, disrupting the execution of the set of instructions and transferring control to handler code to be executed by the first thread unit;

wherein said disrupting is performed by asynchronous user-level signaling hardware.

11. The method of claim 10, wherein:

the set of one or more instructions is a software transaction to be performed atomically.

12. The method of claim 11, wherein:

said handler code is to return a failure indication if said software transaction observes a memory modification to a location that breaks atomicity for the software transaction.

13. The method of claim 10, wherein:

the set of one or more instructions is an atomic multi-compare and single-swap operation.

14. The method of claim 13, wherein:

said handler code is to return a failure indication if said single-swap was not successfully completed before said disruption.

15. The method of claim 10, wherein:

the set of one or more instructions is a first thread.

16. The method of claim 15, wherein:

said write operation is performed by a second thread, the second thread having higher priority than the first thread.

17. The method of claim 16, wherein:

said handler code is further to release a lock held by the first thread.

18. The method of claim 10, wherein:

wherein said transferring is performed without a change in privilege level for the first thread unit

19. An article comprising:

a tangible storage medium having a plurality of machine accessible instructions;

wherein, when the instructions are executed by a processor, the instructions provide for;

enabling monitoring of a memory location;

beginning to perform a set of one or more instructions on a first thread unit;

responsive to a write operation to the memory location by a second thread unit, disrupting the execution of the set of instructions and transferring control to handler code to be executed by the first thread unit;

wherein said disrupting is performed by asynchronous user-level signaling hardware.

20. The article of claim 19, wherein:

the set of one or more instructions is a software transaction to be performed atomically.

21. The article of claim 20, wherein:

said handler code is to return a failure indication if said software transaction observes a memory modification to a location that breaks atomicity for the software transaction.

22. The article of claim 19, wherein:

the set of one or more instructions is an atomic multi-compare and single-swap operation.

23. The article of claim 22, wherein:

said handler code is to return a failure indication if said single-swap was not successfully completed before said disruption.

24. The article of claim 19, wherein:

the set of one or more instructions is a first thread.

25. The article of claim 24, wherein:

said write operation is performed by a second thread, the second thread having higher priority than the first thread.

26. The article of claim 25, wherein:

said handler code is further to release a lock held by the first thread.

27. The article of claim 19, wherein:

wherein said transferring is performed without a change in privilege level for the first thread unit.