Monolithic MEMS and integrated circuit device having a barrier and method of fabricating the same

• US 20080006889A1
• Filed: 06/05/2006
• Published: 01/10/2008
• Est. Priority Date: 06/05/2006
• Status: Active Grant

• Current Assignee: Akustica Incorporated (Robert Bosch GmbH)
• Original Assignee: Akustica Incorporated (Robert Bosch GmbH)
• Inventors: Diamond, Brett M., Zeleznik, Matthew A.
• Granted Patent: US 7,863,714 B2
• Time in Patent Office: Days
• US Class Current: 257/414
• CPC Class Codes: B81B 2201/0257 Microphones or microspeakers
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0778 Topology for facilitating the monolithic integration not provided for in B81C2203/0764 - B81C2203/0771
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit device includes a semiconductor die, the semiconductor die including a semiconductor substrate, driving/control circuitry disposed along a peripheral region of the semiconductor die, a MEMS device disposed within a central region of the semiconductor die, and a barrier disposed between the driving/control circuitry and the MEMS device.

Claims

1. An integrated circuit device, comprising:

a semiconductor die, the semiconductor die including a semiconductor substrate;

driving/sensing circuitry disposed along a peripheral region of the semiconductor die;

a MEMS device disposed within a central region of the semiconductor die; and

a barrier between the driving/sensing circuitry and the MEMS device.

2. The integrated circuit device according to claim 1, wherein the barrier prevents contaminants and moisture from migrating from the MEMS device to the driving/sensing circuitry.

3. The integrated circuit device according to claim 1, wherein the MEMS devices includes one of a microphone, a speaker, an inertial sensor, a pressure sensor, or an RF tunable device.

4. The integrated circuit device according to claim 1, wherein the barrier includes a plurality of interconnection layers and a plurality of conductive vias encircling the MEMS device.

5. The integrated circuit device according to claim 4, wherein the plurality of interconnection layers and the plurality of conductive vias are electrically connected to the semiconductor substrate by a diffusion region within the semiconductor substrate.

6. The integrated circuit device according to claim 4, wherein the plurality of interconnection layers and the plurality of conductive vias are electrically floating.

7. The integrated circuit device according to claim 4, wherein the plurality of interconnection layers and the plurality of conductive vias are electrically connected to one of the MEMS device and the driving/sensing circuitry.

8. The integrated circuit device according to claim 4, wherein the barrier includes at least one conductive line electrically interconnecting the MEMS device and the driving/sensing circuitry.

9. The integrated circuit device according to claim 8, wherein the conductive line extends through the barrier at a position perpendicular to barrier.

10. The integrated circuit device according to claim 9, wherein the conductive line extends through the barrier at a position below the plurality of interconnection layers and the plurality of conductive vias.

11. The integrated circuit device according to claim 8, wherein the conductive line passes through the barrier at an uppermost one of the plurality of interconnection layers.

12. The integrated circuit device according to claim 8, wherein the conductive line passes through the barrier at a lowermost one of the plurality of interconnection layers.

13. The integrated circuit device according to claim 8, wherein the conductive line passes through the barrier at a lowermost one of the plurality of conductive vias.

14. The integrated circuit device according to claim 13, wherein the conductive line includes polysilicon.

15. The integrated circuit device according to claim 8, wherein the conductive line passes beneath the barrier through the substrate.

16. The integrated circuit device according to claim 15, wherein the conductive line includes a diffusion region formed in the substrate.

17. The integrated circuit device according to claim 4, wherein the plurality of interconnection layers are electrically connected to the semiconductor substrate by a diffusion layer within the semiconductor substrate.

18. The integrated circuit device according to claim 4, wherein each of the plurality of interconnection layers are connected to an adjacent one of the plurality of interconnection layers by at least one of the plurality of conductive vias.

19. The integrated circuit device according to claim 4, wherein middle and lowermost ones of the plurality of interconnection layers are electrically interconnected by two of the plurality of conductive vias.

20. The integrated circuit device according to claim 4, wherein a lowermost one of the plurality of interconnection layers is electrically connected to a diffusion region of the semiconductor substrate by two of the plurality of conductive vias.

21. The integrated circuit device according to claim 4, wherein one of oxide and nitride materials separate the plurality of interconnection layers and the plurality of conductive vias.

22. The integrated circuit device according to claim 1, wherein the barrier is covered with a passivation layer.

23. A method of fabricating an integrated circuit device, comprising:

forming driving/sensing circuitry disposed along a peripheral region of a semiconductor die, the semiconductor die including a semiconductor substrate;

forming a MEMS device within a central region of the semiconductor die; and

forming a barrier between the driving/sensing circuitry and the MEMS device.

24. The method according to claim 23, wherein the barrier prevents contaminants and moisture from migrating from the driving/sensing circuitry to the MEMS device.

25. The method according to claim 23, wherein the MEMS devices includes one of a microphone, a speaker, an inertial sensor, a pressure sensor, or an RF tunable device.

26. The method according to claim 23, wherein the forming a barrier includes a formation of a plurality of interconnection layers and a plurality of conductive vias encircling the MEMS device.

27. The method according to claim 26, wherein the plurality of interconnection layers and the plurality of conductive vias are electrically connected to the semiconductor substrate by a diffusion region within the semiconductor substrate.

28. The method according to claim 26, wherein the plurality of interconnection layers and the plurality of conductive vias are electrically floating.

29. The method according to claim 26, wherein the plurality of interconnection layers and the plurality of conductive vias are electrically connected to one of the MEMS device and the driving/control circuitry.

30. The method according to claim 26, wherein the barrier includes at least one conductive line electrically interconnecting the MEMS device and the driving/control circuitry.

31. The method according to claim 30, wherein the conductive line extends through the barrier at a position perpendicular to barrier.

32. The method according to claim 30, wherein the conductive line extends through the barrier at a position below the plurality of interconnection layers and the plurality of conductive vias.

33. The method according to claim 30, wherein the conductive line passes through the barrier at an uppermost one of the plurality of interconnection layers.

34. The method according to claim 30, wherein the conductive line passes through the barrier at a lowermost one of the plurality of interconnection layers.

35. The method according to claim 30, wherein the conductive line passes through the barrier at a lowermost one of the plurality of conductive vias.

36. The method according to claim 35, wherein the conductive line includes polysilicon.

37. The method according to claim 30, wherein the conductive line passes beneath the barrier through the substrate.

38. The method according to claim 37, wherein the conductive line includes a diffusion region formed in the substrate.

39. The method according to claim 26, wherein the plurality of interconnection layers are electrically connected to the semiconductor substrate by a diffusion layer within the semiconductor substrate.

40. The method according to claim 26, wherein each of the plurality of interconnection layers are connected to an adjacent one of the plurality of interconnection layers by at least one of the plurality of conductive vias.

41. The method according to claim 26, wherein middle and lowermost ones of the plurality of interconnection layers are electrically interconnected by two of the plurality of conductive vias.

42. The method according to claim 26, wherein a lowermost one of the plurality of interconnection layers is electrically connected to a diffusion region of the semiconductor substrate by two of the plurality of conductive vias.

43. The method according to claim 26, wherein one of oxide and nitride materials separate the plurality of interconnection layers and the plurality of conductive vias.

44. The method according to claim 23, wherein the barrier is covered with a passivation layer.

45. The method according to claim 23, wherein the MEMS device, the driving/sensing circuitry, and the barrier are monolithically formed on the semiconductor die using CMOS fabrication processes.

47. The method according to claim 23, wherein the MEMS device, the driving/sensing circuitry, and the barrier are simultaneously formed on the semiconductor die.