Packaging of hybrib integrated circuits

• US 20080006939A1
• Filed: 06/18/2007
• Published: 01/10/2008
• Est. Priority Date: 06/19/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Sensors Licensing LLC
• Inventors: Logan, Elizabeth, Ray, Curtis
• Granted Patent: US 7,468,556 B2
• Time in Patent Office: Days
• US Class Current: 257/734
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: G01L 19/141 Monolithic housings, e.g. molded or one-piece housings
• CPC Class Codes: G01L 19/148 Details about the circuit board integration, e.g. integrated with the diaphragm surface or encapsulation
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/1815 Shape
• CPC Class Codes: H01L 2924/30107 Inductance

Abstract

Improved sensor packaging is provided with a hybrid integration approach. In one example, an application specific integrated circuit (ASIC) for sensor signal conditioning is packaged. The ASIC package has an aperture in it that exposes a chip to chip bonding interface of the ASIC chip. The rest of the ASIC chip is surrounded by the package, including the connections between the external package leads and the ASIC chip. A sensor chip, also having a chip to chip bonding interface, is disposed in the package aperture and bonded to the ASIC chip such that the two chip to chip bonding interfaces are connected. Flip chip bonding of the sensor chip to the ASIC chip is a preferred approach for chip to chip bonding. The vertical gap between the two chips can be filled in by an underfill process. The lateral gap between the sensor chip and the package can also be filled.

Claims

1. A hybrid integrated circuit assembly comprising:

a first integrated circuit (IC) chip having a first chip to chip bonding (CCB) interface;

a package having external electrical leads electrically connected to said first IC chip, wherein said package surrounds all connections of said electrical leads to said first IC chip and does not cover said first CCB interface, thereby defining a package aperture;

a second IC chip disposed in said package aperture and having a second CCB interface, wherein said first CCB interface and said second CCB interface are connected.

2. The assembly of claim 1, wherein said second IC chip comprises a microelectromechanical (MEMS) sensor, and wherein said first IC chip comprises sensor signal conditioning circuitry.

3. The assembly of claim 2, wherein said MEMS sensor comprises a pressure sensor.

4. The assembly of claim 1, wherein said first and second CCB interfaces are selected from the group consisting of:

flip chip bonding interface, adhesive bonding interface, anisotropic adhesive bonding interface, gold stud bumping interface, and wire bonding interface.

5. The assembly of claim 1, further comprising a protective metal layer disposed on a top surface of said first IC chip, wherein said protective metal layer extends at least from beneath edges of said second IC chip to beneath said package.

6. The assembly of claim 1, wherein said package provides substantially no mechanical stress to said second IC chip.

7. A method of fabricating a hybrid integrated circuit assembly, the method comprising:

providing a first integrated circuit (IC) chip having a first chip to chip bonding (CCB) interface;

packaging said first IC chip in a package having external electrical leads connected to said first IC chip such that said package surrounds all connections of said electrical leads to said first IC chip and does not cover said first CCB interface, thereby defining a package aperture;

disposing a second IC chip having a second CCB interface in said package aperture such that said first CCB interface and said second CCB interface are connected.

8. The method of claim 7, wherein said disposing a second IC chip is performed after said packaging said first IC chip.

9. The method of claim 7, further comprising filling a lateral gap between said second IC chip and said package.

10. The method of claim 9, wherein said filling a lateral gap comprises filling said lateral gap with a material selected from the group consisting of epoxy glob top materials, gels, and elastomers.

11. The method of claim 7, further comprising filling a vertical gap between said first IC chip and said second IC chip.

12. The method of claim 11, wherein said filling a vertical gap comprises wicking an underfill material into said vertical gap.

13. The method of claim 7, wherein said first and second CCB interfaces are selected from the group consisting of:

flip chip bonding interface, gold stud bumping interface, adhesive bonding interface, anisotropic adhesive bonding interface, and wire bonding interface.

14. The method of claim 7, further comprising depositing a protective metal layer on a top surface of said first IC chip, wherein said protective metal layer extends at least from beneath edges of said second IC chip to beneath said package.

15. The method of claim 7, wherein said package provides substantially no mechanical stress to said second IC chip.