Programming methods to increase window for reverse write 3D cell

• US 20080007989A1
• Filed: 06/25/2007
• Published: 01/10/2008
• Est. Priority Date: 09/28/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Kumar, Tanmay, Petti, Christopher, Herner, S.
• Granted Patent: US 7,800,934 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/33 Material including silicon
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A method of operating a nonvolatile memory cell includes providing the nonvolatile memory cell comprising a diode which is fabricated in a first resistivity, unprogrammed state, and applying a forward bias to the diode having a magnitude greater than a minimum voltage required for programming the diode to switch the diode to a second resistivity, programmed state. The second resistivity state is lower than the first resistivity state.

Claims

1. A method of operating a nonvolatile memory cell, comprising:

providing the nonvolatile memory cell comprising a diode which is fabricated in a first resistivity, unprogrammed state; and

applying a forward bias to the diode having a magnitude greater than a minimum voltage required for programming the diode to switch the diode to a second resistivity, programmed state, wherein the second resistivity state is lower than the first resistivity state.

2. The method of claim 1, wherein the step of applying the forward bias comprising applying the forward bias of at least 5 volts.

3. The method of claim 2, wherein the step of applying the forward bias comprising applying the forward bias of at about 8 to about 12 volts.

4. The method of claim 1, further comprising sensing a resistivity state of the diode as a data state of the memory cell.

5. The method of claim 4, wherein the step of sensing comprises sensing a read current of at least 3.5×

10<sup>−

5</sup> A at a read voltage of at least +1.5V.

6. The method of claim 1, further comprising:

applying a reverse bias to the diode to switch the diode to a third resistivity, unprogrammed state, wherein the third resistivity state is higher than the second resistivity state; and

applying a forward bias to the diode to switch the diode to a fourth resistivity, programmed state, wherein the fourth resistivity state is lower than the third resistivity state.

7. The method of claim 6, wherein:

the step of applying the forward bias comprises applying the forward bias in a factory in which the memory cell is fabricated; and

the step of applying the reverse bias is performed by a user of the memory cell after the memory cell leaves the factory in which the memory cell is fabricated.

8. The method of claim 1, wherein the nonvolatile memory cell consists essentially of the diode and first and second electrically conductive electrodes electrically contacting the diode.

9. The method of claim 1, wherein:

the nonvolatile memory cell consists essentially of first and second electrically conductive electrodes, the diode and an antifuse;

the diode and the antifuse are located in series between the first and the second electrically conductive electrodes; and

the step of applying the forward bias comprises applying the forward bias of at least 8 volts between the first and the second electrically conductive electrodes to form a conductive link breaching a dielectric layer of the antifuse.

10. The method of claim 1, wherein the diode comprises a polycrystalline semiconductor p-i-n diode.

11. A method of operating a nonvolatile memory cell, comprising:

providing the nonvolatile memory cell comprising a diode which is fabricated in a first resistivity, unprogrammed state; and

applying a plurality of forward bias pulses to the diode to switch the diode to a second resistivity, programmed state, wherein the second resistivity state is lower than the first resistivity state.

12. The method of claim 11, further comprising sensing a resistivity state of the diode as a data state of the memory cell.

13. The method of claim 12, wherein the step of sensing comprises sensing a read current of at least 3.5×

10<sup>−

5</sup> A at a read voltage of at least +1.5V.

14. The method of claim 11, further comprising applying a reverse bias to the diode to switch the diode to a third resistivity, unprogrammed state, wherein the third resistivity state is higher than the second resistivity state.

15. The method of claim 14, further comprising applying a forward bias to the diode to switch the diode to a fourth resistivity, programmed state, wherein the fourth resistivity state is lower than the third resistivity state.

16. The method of claim 14, wherein:

the step of applying the plurality of forward bias pulses comprises applying the forward bias pulses in a factory in which the memory cell is fabricated; and

the step of applying the reverse bias is performed after the memory cell leaves the factory in which the memory cell is fabricated.

17. The method of claim 11, wherein the nonvolatile memory cell consists essentially of the diode and first and second electrically conductive electrodes electrically contacting the diode.

18. The method of claim 11, wherein:

The nonvolatile memory cell consists essentially of first and second electrically conductive electrodes, the diode and an antifuse;

the diode and the antifuse are located in series between the first and the second electrically conductive electrodes; and

the step of applying a plurality of forward bias pulses to the diode comprises applying the forward bias pulses between the first and the second electrically conductive electrodes to form a conductive link breaching a dielectric layer of the antifuse.

19. The method of claim 11, wherein the diode comprises a polycrystalline semiconductor p-i-n diode.

20. The method of claim 11, wherein the step of applying a plurality of forward bias pulses comprises applying a plurality of forward bias pulses of at least 5V.