Semiconductor memory device

• US 20080007993A1
• Filed: 07/02/2007
• Published: 01/10/2008
• Est. Priority Date: 07/04/2006
• Status: Abandoned Application

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Sato, Shinichi, Saitoh, Masahiro
• Application Number:
  US11/822,123
• Publication Number:
  US 20080007993A1
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A semiconductor memory device comprises writing means for performing a first writing action for shifting an electric resistance of a variable resistance element from a first state to a second state by applying a first voltage between both ends of a memory cell and a gate potential to a gate of a cell access transistor, and a second writing action for shifting the electric resistance from the second state to the first state by applying a second voltage having a polarity opposite to that of the first voltage between both ends of the memory cell and a gate potential to the gate of the cell access transistor, and the polarity and absolute value of the voltage to be applied to both ends of the variable resistance element in the memory cell to be written in the first writing action is different from those in the second writing action.

Claims

1. A semiconductor memory device comprising:

a memory cell having a variable resistance element having two terminals and being capable of storing information in accordance with a shift of an electric resistance between a first state and a second state by applying voltages having different polarities to both ends respectively and a cell access transistor having a source or a drain connected to one end of the variable resistance element; and

writing means for performing two writing actions such as a first writing action shifting the electric resistance of the variable resistance element from the first state to the second state by applying a predetermined first voltage between both ends of the memory cell and a predetermined gate potential to a gate of the cell access transistor, and a second writing action shifting the electric resistance of the variable resistance element from the second state to the first state by applying a predetermined second voltage having a polarity opposite to that of the first voltage between both ends of the memory cell and a predetermined gate potential to the gate of the cell access transistor, wherein

the polarity and an absolute value of the voltage to be applied to both ends of the variable resistance element in the memory cell to be written in the first writing action are different from those in the second writing action.

2. The semiconductor memory device according to claim 1, wherein

the polarity and absolute value of a voltage at both ends between the source and drain of the cell access transistor in the memory cell to be written in the first writing action are different from those in the second writing action.

3. The semiconductor memory device according to claim 2, wherein

a bias condition of the cell access transistor in each of the first writing action and the second action is set such that the absolute value of the voltage at both ends between the source and the drain of the cell access transistor in the memory cell to be written in either one of the first writing action or the second writing action is smaller than that in the other writing action when the absolute value of the voltage at both ends of the variable resistance element in the memory cell to be written is greater than that in the other writing action.

4. The semiconductor memory device according to claim 1, wherein

absolute values of the first voltage and the second voltage are the same.

5. The semiconductor memory device according to claim 1, wherein

the cell access transistor is an enhancement-type N channel MOSFET.

6. The semiconductor memory device according to claim 5, wherein

the higher one of potentials at both ends of the memory cell to be written is the same level as a gate potential of the cell access transistor in the memory cell to be written in the first writing action.

7. The semiconductor memory device according to claim 5, wherein

the higher one of potentials at both ends of the memory cell to be written is the same level as a gate potential of the cell access transistor in the memory cell to be written in the second writing action.

8. The semiconductor memory device according to claim 5, wherein

the higher one of potentials at both ends of the memory cell to be written is the same level as a gate potential of the cell access transistor in the memory cell to be written in the first writing action and

the higher one of potentials at both ends of the memory cell to be written is the same level as the gate potential of the cell access transistor in the memory cell to be written in the second writing action.

9. The semiconductor memory device according to claim 5, wherein

the higher one of potentials at both ends of the memory cell to be written in the first writing action is the same level as that of the second writing action.

10. The semiconductor memory device according to claim 5, wherein

the gate potential of the cell access transistor in the memory cell to be written in the first writing action is the same level as that in the second writing action.

11. The semiconductor memory device according to claim 5, wherein

the higher one of potentials at both ends of the memory cell to be written in the first writing action is the same level as that of the second writing action and

the gate potential of the cell access transistor in the memory cell to be written in the first writing action is the same level as that in the second writing action.

12. The semiconductor memory device according to claim 1 comprising:

a memory cell array including the memory cells arranged in a row and column direction, wherein

the gates of the cell access transistors in the memory cells arranged in a row are connected to a common word line extending in the row direction, one ends of the memory cells arranged in a column are connected to a common bit line extending in the column direction, the other ends of the memory cells are connected to a source line extending in the row or column direction, and

the writing means applies the first voltage between the bit line and the source line connected to the memory cell to be written and applies the predetermined gate potential to the word line connected to the gate of the cell access transistor in the memory cell to be written in the first writing action, and applies the second voltage between the bit line and the source line connected to the memory cell to be written and applies the predetermined gate potential to the word line connected to the gate of the cell access transistor in the memory cell to be written in the second writing action.

13. The semiconductor memory device according to claim 1, wherein

a thickness of the gate insulation film of the cell access transistor is the same as that of the gate insulation film of a transistor constituting at least the writing means.