Architecture, System and Method for Compressing Repair Data in an Integrated Circuit (IC) Design

• US 20080008015A1
• Filed: 06/22/2007
• Published: 01/10/2008
• Est. Priority Date: 06/23/2006
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Zorian, Yervant, Mkhoyan, Mher, Torjyan, Gevorg, Darbinyan, Karen
• Granted Patent: US 7,898,882 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/802 by encoding redundancy signals

Abstract

Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances.

Claims

1. A repair data storage method operable with an integrated circuit (IC) design having a plurality of memory instances, comprising:

determining repair data for each of said plurality of memory instances;

compressing said repair data into a compressed repair data format; and

storing said compressed repair data format into a shared nonvolatile storage (NVS) common to said plurality of memory instances.

2. The repair data storage method as set forth in claim 1, wherein said repair data is determined by running one or more tests by a test and repair processor (TRP) associated with said plurality of memory instances.

3. The repair data storage method as set forth in claim 1, wherein said plurality of memory instances are organized into a number of embedded memory systems, each memory system having a TRP associated therewith for performing one or more tests with respect to a sub-plurality of memory instances thereof.

4. The repair data storage method as set forth in claim 1, wherein said repair data is compressed “

on the fly”

by a shared NVS processor as said repair data is scanned out from a group of registers associated with said plurality of memory instances.

5. The repair data storage method as set forth in claim 1, wherein said repair data is compressed based on a particular fault distribution model.

6. The repair data storage method as set forth in claim 5, wherein said particular fault distribution model comprises a random distribution model.

7. The repair data storage method as set forth in claim 5, wherein said particular fault distribution model comprises a clustered distribution model.

8. The repair data storage method as set forth in claim 1, wherein said compressed repair data format is stored into a plurality of electrically programmable fuses (E-fuses) forming said shared NVS.

9. The repair data storage method as set forth in claim 1, wherein said compressed repair data format is stored into a plurality of laser programmable fuses (L-fuses) forming said shared NVS.

10. An integrated circuit (IC) design, comprising:

a plurality of embedded memory systems each having a plurality of memory instances, wherein each memory instance is associated with a reconfiguration register and a repair register;

a shared nonvolatile storage (NVS) container disposed outside said embedded memory systems, said shared NVS container for storing compressed repair data associated with said plurality of embedded memory systems;

a shared NVS processor for executing a compression engine operable to compress repair data scanned out from each of said repair registers; and

a serial interconnection for interfacing said plurality of embedded memory systems with said shared NVS processor.

11. The IC design as set forth in claim 10, wherein said shared NVS container comprises a plurality of electrically programmable fuses (E-fuses).

12. The IC design as set forth in claim 10, wherein said shared NVS container comprises a plurality of laser programmable fuses (L-fuses).

13. The IC design as set forth in claim 10, wherein each embedded memory system is associated with a corresponding test and repair processor (TRP).

14. The IC design as set forth in claim 10, wherein said compression engine is operable to compress said repair data based on a particular fault distribution model.

15. The IC design as set forth in claim 10, wherein said plurality of memory instances are selected from dynamic random access memory (DPAM) instances, static random access memory (SRAM) instances, nonvolatile memory instances, and programmable memory instances.

16. A coding method for coding repair data, wherein said method is operable with an integrated circuit (IC) design having a plurality of memory instances, comprising:

grouping a plurality of data segments corresponding to said repair data into a number of groups, each group containing a set of data segments, wherein said repair data is obtained from testing said plurality of memory instances;

providing a first level indication for each group to indicate if at least one data segment thereof comprises active repair data; and

if a particular group has at least one data segment that comprises active repair data, providing a second level indication with respect to all data segments in said particular group that have active repair data therein.

17. The coding method for coding repair data as set forth in claim 16, further comprising:

providing a flag for said particular group to indicate if additional data segments within said particular group have active repair data therein.

18. The coding method for coding repair data as set forth in claim 16, wherein said first level indication comprises a Group Change Flag (GCF).

19. The coding method for coding repair data as set forth in claim 16, wherein said second level indication comprises an address element corresponding to a data segment having active repair data.

20. The coding method for coding repair data as set forth in claim 16, wherein said second level indication comprises an Enable Flag (EF) corresponding to a data segment having active repair data.

21. A system for effectuating repair data storage in an integrated circuit (IC) design having a plurality of memory instances, comprising:

means for determining repair data for each of said plurality of memory instances;

means for compressing said repair data into a compressed repair data format; and

means for storing said compressed repair data format, wherein said means for storing is shared by said plurality of memory instances.

22. The system as set forth in claim 21, wherein said means for determining repair data is operable by running one or more tests by a test and repair processor (TRP) associated with said plurality of memory instances.

23. The system as set forth in claim 21, wherein said plurality of memory instances are organized into a number of embedded memory systems, each memory system having a TRP associated therewith for performing one or more tests with respect to a sub-plurality of memory instances thereof.

24. The system as set forth in claim 21, wherein said means for compressing comprises a compression engine executing on a shared processor, said compression engine operating to compress said repair data “

on the fly”

as said repair data is scanned out from a group of registers associated with said plurality of memory instances.

25. The system as set forth in claim 21, wherein said means for storing said compressed repair data format comprises a plurality of electrically programmable fuses (E-fuses).

26. The system as set forth in claim 21, wherein said means for storing said compressed repair data format comprises a plurality of laser programmable fuses (L-fuses).