Systems and methods for equalization of received signals in a wireless communication network

• US 20080008234A1
• Filed: 08/08/2007
• Published: 01/10/2008
• Est. Priority Date: 12/06/2001
• Status: Abandoned Application

• Current Assignee: Intellectual Ventures Holding 73 LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Holding 73 LLC (Intellectual Ventures LLC)
• Inventors: Lakkis, Ismail
• Application Number:
  US11/890,998
• Publication Number:
  US 20080008234A1
• Time in Patent Office: Days
• US Class Current: 375/233
• CPC Class Codes: H04B 1/71637 Receiver aspects H04B1/7183 takes precedence
• CPC Class Codes: H04B 1/7183 Synchronisation
• CPC Class Codes: H04B 1/719 Interference-related aspects
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

An equalizer comprising a hard decision block which feeds a FEC block and a shift register, which uses past estimates during a first iteration. The output of the FEC block is fed back to the shift register during a subsequent iteration to fully remove any inter chip interference.

Claims

1. An equalizer comprising:

a hard decision estimation block configured to generate a hard decision estimate of input sample;

a past decision block configured to multiply past decision estimates with associated coefficients; and

a future decision block configured to multiply future decision estimates with associated coefficients.

2. The equalizer of claim 1, wherein the hard decision estimate is fed to the past decision block during a first iteration.

3. The equalizer of claim 2, wherein the past decision block is fed by the future decision block during a second iteration.

4. The equalizer of claim 1, wherein the hard decision estimate is fed to a forward error correction block.

5. The equalizer of claim 4, wherein the future decision block is fed by the forward error correction block.

6. The equalizer of claim 1, wherein the output of the past decision block is subtracted from the input of the hard decision estimation block during a first iteration.

7. The equalizer of claim 6, wherein the output of the future decision block is combined with the output of the past decision block, and wherein the combined outputs are subtracted form the input of the hard decision estimation block during a second iteration.

8. A receiver, comprising:

a serial to parallel converter configured to receive a parallel data stream and convert it into a plurality of parallel data streams;

a plurality of matched filters coupled with the serial to parallel converter, the plurality of matched filters configured to match each of the parallel data streams;

a combiner configured to combine the matched parallel data streams; and

an equalizer comprising;

a hard decision estimation block configured to generate a hard decision estimate of input sample;

a past decision block configured to multiply past decision estimates with associated coefficients; and

a future decision block configured to multiply future decision estimates with associated coefficients.

9. The receiver of claim 8, wherein the hard decision estimate is fed to the past decision block during a first iteration.

10. The receiver of claim 9, wherein the past decision block is fed by the future decision block during a second iteration.

11. The receiver of claim 8, further comprising a forward error correction block coupled with the equalizer, wherein the hard decision estimate is fed to a forward error correction block.

12. The receiver of claim 11, wherein the future decision block is fed by the forward error correction block.

13. The receiver of claim 8, wherein the output of the past decision block is subtracted from the input of the hard decision estimation block during a first iteration.

14. The receiver of claim 13, wherein the output of the future decision block is combined with the output of the past decision block, and wherein the combined outputs are subtracted from the input of the hard decision estimation block during a second iteration.

15. The receiver of claim 12, wherein the forward error correction block is configured to detect errors in the hard decision estimate produced by the hard decision estimation block, and wherein the forward error correction block is further configured to only feed data back to the future estimation block if errors are detected.