GRAPHICAL LANGUAGE COMPILER SYSTEM

• US 20080010049A1
• Filed: 07/13/2007
• Published: 01/10/2008
• Est. Priority Date: 06/29/2006
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Smith, Gary, Pouchak, Michael
• Granted Patent: US 8,418,128 B2
• Time in Patent Office: Days
• US Class Current: 703/014
• CPC Class Codes: F24F 11/30 for purposes related to the operation of the system, e.g. for safety or monitoring
• CPC Class Codes: F24F 11/46 Improving electric energy efficiency or saving
• CPC Class Codes: F24F 11/526 giving audible indications
• CPC Class Codes: F24F 11/63 Electronic processing
• CPC Class Codes: F24F 11/88 Electrical aspects, e.g. circuits
• CPC Class Codes: G05B 19/0426 Programming the control sequence
• CPC Class Codes: G05B 2219/23258 GUI graphical user interface, icon, function bloc editor, labview
• CPC Class Codes: G05B 2219/23266 Compiler
• CPC Class Codes: G05B 2219/23306 Load program from host, remote load, non volatile card to volatile, ram
• CPC Class Codes: G05B 2219/23452 Simulate sequence on display to control program, test functions
• CPC Class Codes: G05B 2219/25257 Microcontroller
• CPC Class Codes: G05B 2219/25265 Flash memory
• CPC Class Codes: G05B 2219/2614 HVAC, heating, ventillation, climate control
• CPC Class Codes: G06F 8/34 Graphical or visual programming
• CPC Class Codes: G06F 9/44 Arrangements for executing specific programs

Abstract

A system having a graphical compiler connected to a function block engine. The graphical compiler may convert graphical information to non-graphical information. A resources allocation module may be connected to the function block engine and the compiler. Also, a function block execution list may be connected to the compiler and the function block engine. A user interface may be connected to the compiler.

Claims

1. A control system language compiler method comprising:

loading control functions into a memory;

initiating a control loop design structure; and

instantiating the control loop design structure.

2. The method of claim 1, further comprising entering a configuration mode of the control loop design structure for designing a circuit or structure.

3. The method of claim 2, further comprising:

designing a circuit or structure which includes dragging function and/or non-function blocks onto a display screen; and

connecting the function and/or non-function blocks to effect a design of the circuit or structure.

4. The method of claim 3, further comprising compiling graphical information of the design of the circuit or structure into information in a non-graphical format.

5. The method of claim 4, wherein the non-graphical format is a comma separated value format.

6. The method of claim 3, further comprising compiling graphical information of the design into a configuration file.

7. The method of claim 4, further comprising allocating memory resources for the information in the non-graphical format.

8. The method of claim 7, further comprising:

providing a tool storage file; and

storing the information of the non-graphical format in the tool storage file.

9. The method of claim 8, further comprising:

entering a simulation mode for testing the design of the circuit or structure; and

making configuration, parameter, summary and/or debug files.

10. A system comprising:

a function block engine; and

a graphical compiler module connected to the function block engine.

11. The system of claim 10, further comprising a function block allocation resources module connected to the function block engine and the graphical compiler module.

12. The system of claim 10, further comprising a function block execution list module connected to the graphical compiler module.

13. The system of claim 10, further comprising a user interface connected to the graphical compiler module.

14. The system of claim 10, wherein the graphical compiler module comprises converting graphical information into non-graphical information.

15. A method comprising:

initiating a graphical compiler module structure;

configuring function blocks, parameters, interconnects, and the like for the graphical compiler module;

activating a memory resource module; and

generating configuration information for the function blocks.

16. The method of claim 15, further comprising generating configuration information for non-function blocks.

17. The method of claim 16, further comprising translating graphical design information into function blocks configuration information.

18. The method of claim 17, further comprising translating graphical design information into non-function block configuration information.

19. The method of claim 18, further comprising converting the function block and non-function block configuration information into an intermediate format.

20. The method of claim 19, wherein the intermediate format is a comma separated value format.