Cache reconfiguration based on run-time performance data or software hint

• US 20080010408A1
• Filed: 07/05/2006
• Published: 01/10/2008
• Est. Priority Date: 07/05/2006
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Sinharoy, Balaram, Tremaine, Robert B., Shen, Xiaowei, Wisniewski, Robert W.
• Granted Patent: US 7,467,280 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

Claims

1. A method for reconfiguring cache memory, comprising:

analyzing one or more characteristics of an execution entity accessing a cache memory;

and reconfiguring the cache dynamically based on the one or more characteristics analyzed, the step of reconfiguring including modifying associativity of the cache memory, modifying amount of the cache memory available to store data, changing coherence granularity of the cache memory, or modifying line size of the cache memory, or combination thereof.

2. The method of claim 1, wherein the one or more characteristics of an execution entity include size of data structure used by the execution entity, expected reference pattern of the execution entity, heat generated by the execution entity, or combination thereof.

3. The method of claim 1, wherein the step of analyzing includes reading temperature data associated with the execution entity to determine amount of heat generated by the execution entity.

4. The method of claim 1, wherein the step of reconfiguring includes changing number of masked bits for mapping into cache memory to modify cache memory associativity.

5. The method of claim 1, wherein the step of reconfiguring includes:

dividing a cache line in the cache memory into a plurality of sectors; and

accessing data of the cache line by one or more sectors.

6. The method of claim 5, further including:

instructing hardware as to which memory region should be cached by sectors and which memory region should be cached by entire cache lines.

7. The method of claim 5, further including:

associating an access bit with each sector of a cache line; and

setting an access bit to true if a processing element uses data of a sector associated with the access bit.

8. The method of claim 7, wherein the step of associating includes:

associating an access bit with each sector of a cache line in level-1 cache.

9. The method of claim 5, further including:

associating a granularity bit with each sector of a cache line, the granularity bit for indicating whether a sector should be cached when one or more other sectors in the cache line are cached.

10. The method of claim 9, wherein the step of associating includes:

associating a granularity bit with each sector of a cache line in level-2 cache, the granularity bit for indicating whether a sector should be cached when one or more other sectors in the cache line are cached.

11. The method of claim 1, wherein the step of analyzing is performed on-line while the execution entity is being run.

12. The method of claim 1, wherein the step of analyzing is performed off-line.

13. The method of claim 1, wherein the step of analyzing is performed by software.

14. The method of claim 1, wherein the step of analyzing is performed by an operating system.

15. A system for reconfiguring cache memory, comprising:

a means for analyzing one or more characteristics of an execution entity accessing a cache memory; and

a means for reconfiguring the cache dynamically based on the one or more characteristics analyzed, the means for reconfiguring including a means for modifying associativity of the cache memory, modifying amount of the cache memory available to store data, changing coherence granularity of the cache memory, or modifying line size of the cache memory, or combination thereof.

16. The system of claim 15, wherein the one or more characteristics of an execution entity include size of data structure used by the execution entity, expected reference pattern of the execution entity, heat generated by the execution entity, or combination thereof.

17. The system of claim 15, wherein the means for analyzing includes a means for reading temperature data associated with the execution entity to determine amount of heat generated by the execution entity.

18. A system for reconfiguring cache memory, comprising:

lower-level cache memory comprising at least a plurality of cache lines, at least one of the cache lines divided into a plurality of sectors;

an access bit associated with each of the plurality of sectors of the lower-level cache memory, the access bit representing whether data of a sector associated with the access bit was used;

higher-level cache memory comprising at least a plurality of cache lines, at least one of the cache lines divided into a plurality of sectors;

a granularity bit associated with each of the plurality of sectors of the higher-level cache memory, the granularity bit representing whether data of a sector associated with the granularity bit should be cached when one or more of other sectors in the same cache line are cached into the lower-level cache memory;

a processor operable to use data of one or more sectors of the lower-level cache memory, the processor further operable to update one or more access bit respectively associated with the one or more sectors; and

means operable to update one or more granularity bits.

19. The system of claim 18, wherein the means operable to update one or more granularity bits includes software.

20. The system of claim 18, wherein the means operable to update one or more granularity bit is operable to update one or more granularity bits based on an analysis performed on an execution entity.