Read/Write Permission Bit Support for Efficient Hardware to Software Handover

• US 20080010417A1
• Filed: 09/24/2007
• Published: 01/10/2008
• Est. Priority Date: 04/28/2006
• Status: Abandoned Application

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Moore, Kevin, Landin, Anders, Hagersten, Erik, Zeffer, Hakan
• Application Number:
  US11/859,955
• Publication Number:
  US 20080010417A1
• Time in Patent Office: Days
• US Class Current: 711/144
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0822 Copy directories local copy tags for implementing a bus snooping protocol G06F12/0831
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

In one embodiment, a method comprises communicating with one or more other nodes in a system from a first node in the system in response to a trap experienced by a processor in the first node during a memory operation, wherein the trap is signalled in the processor in response to one or more permission bits stored with a cache line in a cache accessible during performance of the memory operation; determining that the cache line is part of a memory transaction in a second node that is one of the other nodes, wherein a memory transaction comprises two or more memory operations that appear to execute atomically in isolation; and resolving a conflict between the memory operation and the memory transaction.

Claims

1. A method comprising:

communicating with one or more other nodes in a system from a first node in the system in response to a trap experienced by a processor in the first node during a memory operation, wherein the trap is signalled in the processor in response to one or more permission bits stored with a cache line in a cache accessible during performance of the memory operation;

determining that the cache line is part of a memory transaction in a second node that is one of the other nodes, wherein a memory transaction comprises two or more memory operations that appear to execute atomically in isolation; and

resolving a conflict between the memory operation and the memory transaction.

2. The method as recited in claim 1 wherein resolving the conflict comprises delaying the memory operation until the memory transaction in the second node completes.

3. The method as recited in claim 1 wherein the memory operation is part of a local memory transaction in the first node, and wherein the conflict is between the local memory transaction and the memory transaction in the second node.

4. The method as recited in claim 3 wherein resolving the conflict comprises aborting the local memory transaction.

5. The method as recited in claim 3 wherein resolving the conflict comprises aborting the memory transaction in the second node.

6. The method as recited in claim 1 wherein the one or more permission bits comprise a read permission bit indicating whether or not the first node has read permission to the respective cache line and a write permission bit indicating whether or not the first node has write permission to the respective cache line.

7. The method as recited in claim 1 further comprising updating the permission bits for the respective cache line responsive to the resolving.

8. The method as recited in claim 1 further comprising using the permission bits to ensure coherence of the respective cache line.

9. The method as recited in claim 8 further comprising:

trapping a load memory operation responsive to the permission bits indicating that the first node does not have read permission to the respective cache line;

coherently transferring the respective cache line to the first node; and

updating the permission bits to indicate read permission.

10. The method as recited in claim 8 further comprising:

trapping a store memory operation responsive to the permission bits indicating that the first node does not have write permission to the respective cache line;

coherently transferring the respective cache line to the first node; and

updating the permission bits to indicate write permission.

11. The method as recited in claim 1 further comprising using the permission bits to trap memory accesses during debugging.

12. The method as recited in claim 1 further comprising using the permission bits to trap memory accesses during simulation.

13. The method as recited in claim 1 further comprising using the permission bits to set watch points at a cache line granularity.

14. A computer accessible storage medium store a plurality of instructions that are executable to perform a method comprising:

communicating with one or more other nodes in a system from a first node in the system in response to a trap experienced by a processor in the first node during a memory operation, wherein the trap is signalled in the processor in response to one or more permission bits stored with a cache line in a cache accessible during performance of the memory operation;

determining that the cache line is part of a memory transaction in a second node that is one of the other nodes, wherein a memory transaction comprises two or more memory operations that appear to execute atomically in isolation; and

resolving a conflict between the memory operation and the memory transaction.

15. The computer accessible storage medium as recited in claim 14 wherein the method further comprises updating the permission bits for the respective cache line responsive to the resolving.

16. The computer accessible storage medium as recited in claim 14 wherein the method further comprises using the permission bits to ensure coherence of the respective cache line.

17. A cache comprising:

a tag memory configured to store a plurality of cache tags, wherein each cache tag corresponds to a respective cache line of data stored in the cache, and wherein each cache tag comprises one or more bits that indicate whether or not a memory operation to the respective cache line is to be trapped in a processor that performs the memory operation; and

a cache control unit coupled to the tag memory and configured to signal a trap for a memory operation responsive to the bits from the cache tag.

18. The cache as recited in claim 17 wherein the one or more bits comprise a read permission bit indicating whether or not a node that includes the cache has read permission to the respective cache line and a write permission bit indicating whether or not the node has write permission to the respective cache line.

19. The cache as recited in claim 18 wherein the cache control unit is configured to signal the trap for a load memory operation responsive to the read permission bit indicating no read permission.

20. The cache as recited in claim 18 wherein the cache control unit is configured to signal the trap for a store memory operation responsive to the write permission bit indicating no write permission.

21. The cache as recited in claim 17 wherein the one or more bits are also stored with the respective cache line in a main memory system, and wherein the one or more bits are loaded into the cache with the respective cache line.