Disabling portions of memory with non-deterministic errors

• US 20080010566A1
• Filed: 06/21/2006
• Published: 01/10/2008
• Est. Priority Date: 06/21/2006
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Benoit, John, Srivastava, Durgesh, Shoemaker, Jonathan, Chang, Tsung-Yung (Jonathan)
• Application Number:
  US11/472,870
• Publication Number:
  US 20080010566A1
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G06F 11/1024 Identification of the type of error
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 29/883 using a single defective memory device with reduced capacity, e.g. half capacity

Abstract

Systems and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Various techniques are provided for detecting a defect in a portion of memory and dynamically avoiding future attempts to access the defective portion of memory. More specifically, the techniques detect and avoid both hard and erratic errors.

Claims

1. A method comprising:

detecting a defect in a portion of memory;

designating said portion of memory as defective; and

avoiding attempts to access said portion of memory designated as defective.

2. The method of claim 1 wherein said designating comprises:

storing data identifying said portion of memory as defective.

3. The method of claim 2 wherein said avoiding comprises:

accessing said stored data and based on said stored data avoiding attempts to access said portion of memory.

4. The method of claim 2 further comprising:

accessing said stored data upon a request to access said memory.

5. The method of claim 2 further comprising:

storing said data within a tag array.

6. The method of claim 2 further comprising:

storing said data within a replacement array.

7. The method of claim 2 further comprising:

storing said data as part of MESI data.

8. The method of claim 1 wherein said detecting said defect comprises:

detecting a hard error for said portion of memory.

9. The method of claim 1 wherein said detecting said defect comprises at least one of the following:

detecting a latent defect;

detecting a multi-cell defect; and

detecting an intermittent or marginal defect.

10. The method of claim 1 further comprising:

receiving a designation of a number of acceptable defects detected in said memory before service is required.

11. A system comprising:

a memory;

defect detection logic to detect defects in said memory;

data structure to store data designating a portion of memory as defective; and

access control logic to control access to said memory, wherein based at least in part on said data structure said access control logic avoids attempts to access said portion of memory designated as defective.

12. The system of claim 11 wherein said defect detection logic comprises error correction coding (ECC) logic.

13. The system of claim 11 wherein said defect detection logic comprises logic to detect a hard error for an address of said memory.

14. The system of claim 13 wherein said defect detection logic determines an address of memory for which a hard error is detected as being defective.

15. The system of claim 11 wherein said data structure comprises a tag array.

16. The system of claim 11 wherein said data structure comprises a replacement array.

17. The system of claim 11 wherein said data structure comprises MESI data for said memory.

18. The system of claim 11 wherein said system comprises point-to-point interconnect.

19. The system of claim 11 wherein the system comprises a front side bus.

20. The system of claim 11, wherein an external interconnect circuit to send audio data from a processor;

and

an audio input/output device to receive said audio data.

21. An apparatus comprising:

a memory; and

a defect detection logic coupled to said memory, wherein said defect detection logic comprises logic to determine an address of memory for which a hard error is detected as being defective.

22. The apparatus of claim 21, further comprising an error detection module coupled to memory, wherein the error detection module to detect errors in portions of memory.

23. The apparatus of claim 22, wherein the defect detection logic to determine if errors detected by the error detection module contain defects.

24. The apparatus of claim 23, wherein the defect detection logic further comprises an error tracking module to track data regarding the errors detected in the memory.

25. The apparatus of claim 24, wherein the defect detection logic further comprises a defect determination module to determine if detected error indicates defect in portion of memory based on data in the error tracking module.

26. The apparatus of claim 25 further comprising a memory control to move the data in the defective portion of memory.

27. The apparatus of claim 25 further comprising an engine module coupled to the memory, wherein the engine module to determine if the portion of memory is to be disabled.

28. The apparatus of claim 27, wherein the engine module further comprises a tag array, wherein the tag array to store set and way data for the portion of memory determined to be defective.